Intel Embedded Intel486 Hardware Reference Manual page 180

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
Bidirectional
Data Buffers
8
BE3#
8
Intel486™
BE2#
Processor
Interface
8
BE1#
8
BE0#
Figure 7-4. Intel486™ Processor Interface to 8-Bit Device
In this example of a 32-bit write, the BE3#–BE0# are enabled; hence 32 bits of data reside on the
data buffer outputs. This data is then swapped based on the control signals. Buffers are enabled
in the following manner:
For Byte # 0 Buffer 3 is enabled (BE0# is true)
For Byte # 1 Buffer 2 and 4 are enabled (BE1# and BEN8H#)
For Byte # 2 Buffer 1 and 5 are enabled (BE2# and BEN8UL#)
For Byte # 3 Buffer 0 and 6 are enabled (BE3# and BEN8UH#)
Table 7-5 shows the truth table for 8-bit I/O interface to the Intel486 processor. The table also
contains the values of the control signals used to enable the second set of buffers. The PLD equa-
tions used to implement these signals are shown in
7-8
BUFF
0
BUFF
1
BUFF
2
BUFF
3
4
BEN8H#
5
BEN8UL# BEN8UH#
Tables 7-3 and 7-4.
8-Bit
Bus
6
A5283-02