Bus Characteristics - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
BLAST#
KEN#
DATA
BRDY#
Some memory devices may be slow enough that 16-byte cycles are undesirable. In this case more
than three wait states exist. The KEN# signal can be deactivated prior to returning RDY# or
BRDY# if three or more wait states are present. As a result, these slow cycles are not converted
to 16-byte cache line fills.
5.2.3

Bus Characteristics

The internal cache causes other effects that impact the memory subsystem design. Perhaps the
most obvious of these is the effect on bus traffic. The fact that the internal cache uses the write-
through policy dramatically increases the number of write bus cycles.
effect. The chart on the left shows the bus cycle mix for an application executed with the
Intel386 DX CPU. The chart on the right shows the same application executed with the Intel486
processor. The percentage of write bus cycles jumps to 70% from 30% when this application is
executed with the Intel486 processor.
5-4
T1 T2 T2
Sampled
here
1
Figure 5-2. Burst Cycle: KEN# Normally Active
T2 T2
Sampled here
2 3 4
Figure 5-3
A5243-01
illustrates this