Associativity And Performance Issues - Intel Embedded Intel486 Hardware Reference Manual

dated later. This allows the CPU to begin the next cycle without being delayed by the main mem-
ory write access time. Both these memory updating techniques are discussed later in this chapter.
6.3.2

Associativity and Performance Issues

Data and instructions are written into the cache by a function that maps the main memory address
into a cache location. The placement policy determines the mapping function from the main
memory address to the cache location. There are four policies to consider: fully associative, di-
rect-mapped, set associative, and sector buffering.
Fully Associative: A fully associative cache system provides maximum flexibility in determining
which blocks are stored in the cache at any time. Ideally, the blocks of words in the cache would
contain the main memory locations needed most by the processor regardless of the distance be-
tween the words in main memory. The size of a block in the cache is also known as the line size,
and corresponds to the width of a cache word. For example, a block can be eight bytes for a 32-
bit processor, in which case two doublewords are accessed each time the cache line is filled. In
the example shown in
31
32-Bit
Cache/DRAM
Processor
Address
FFFFFC
000000
FFFFF4
128
Locations
16339C
FFFFF8
28 16 Bit SRAM
Figure 6-1. A Fully Associative Cache Organization
Because there is no single relationship between all of the addresses in the 64 blocks, the cache
would have to store the entire address of each block. When the processor requests data, the cache
Figure 6-1, the block size is one doubleword.
24
TAG
Select
16 MByte DRAM = 24 Bits
TAG– Data–
22 Bits 4 Bytes
24682468
12345678
33333333
87654321
11223344
4096 Bit SRAM
CACHE SUBSYSTEM
2 1 0
Byte Enable
Data
24682468
11223344
33333333
87654321
12345678
32 Bits
16 Mbyte DRAM
FFFFFC
FFFFF8
FFFFF4
1633A0
16339C
163398
00000C
000008
000004
000000
6-5