Intel Embedded Intel486 Hardware Reference Manual page 291

High-speed CMOS logic families have much higher edge rates than slower logic technologies.
The switching speeds and drive capability for high performance also increase noise levels. The
switching activity of one device can propagate to other devices through the power supply. For
example, in the TTL NAND gate shown in
on for a short time while the output is switching. This increased loading causes a negative spike
on V and a positive spike on V
CC
A
B
D1
In synchronous systems where several gates switch simultaneously, the result is a significant
amount of noise on the power and ground lines. This noise can be removed by decoupling the
power supply. First, it is necessary to match the power supply's impedance to that of the individ-
ual components. Any power supply presents a low source impedance to other circuits, whether
they are individual components on the same board or other boards in a multi-board system. It is
necessary to match the supply's impedance to that of the components in order to lessen the poten-
tial for voltage drops that can be caused by IC edge rates, ground- or signal-level shifting, noise
induced currents or voltage reflections.
This mismatch can be minimized using suitable high-frequency capacitors for bulk decoupling
of major circuitry sections, or for decoupling entire printed circuit boards in multi-board systems.
This capacitor is typically placed at the supply's entry point to the board. It should be an alumi-
num or tantalum-electrolytic type capacitor with a low equivalent series capacitance and low
equivalent series inductance. This capacitor's value is typically 10 to 47 µ F. Placing several ca-
pacitors in parallel provides the lowest effective series resistance (ESR) in the system. Additional
0.1 µ F capacitors may be needed if supply noise is still a problem.
Additional decoupling capacitors can be used across the devices between V
voltage spikes that occur due to the switching of gates are reduced since the extra current required
PHYSICAL DESIGN AND SYSTEM DEBUGGING
Figure
.
SS
V
CC
R1
Q1
D2
Figure 10-4. Circuit without Decoupling
10-4, both the Q3 and the Q4 transistors are
R2
Q2 Q3
Q4
R4
R3
D3
Y
and V lines. The
CC SS
10-7