Intel Embedded Intel486 Hardware Reference Manual page 68

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
each bus cycle. BS8# and BS16# must be deasserted when addressing 32-bit devices. An 8-bit
bus width is selected if both BS16# and BS8# are asserted.
BS16# and BS8# force the Intel486 processor to run additional bus cycles to complete requests
larger than 16 or 8 bits. A 32-bit transfer is converted into two 16-bit transfers (or 3 transfers if
the data is misaligned) when BS16# is asserted. Asserting BS8# converts a 32-bit transfer into
four 8-bit transfers.
Extra cycles forced by BS16# or BS8# should be viewed as independent bus cycles. BS16# or
BS8# must be asserted during each of the extra cycles unless the addressed device has the ability
to change the number of bytes it can return between cycles.
The Intel486 processor drives the byte enables appropriately during extra cycles forced by BS8#
and BS16#. A31–A2 does not change if accesses are to a 32-bit aligned area.
set of byte enables that is generated on the next cycle for each of the valid possibilities of the byte
enables on the current cycle.
The dynamic bus sizing feature of the Intel486 processor is significantly different than that of the
Intel386™ processor. Unlike the Intel386 processor, the Intel486 processor requires that data
bytes be driven on the addressed data pins. The simplest example of this function is a 32-bit
aligned, BS16# read. When the Intel486 processor reads the two high order bytes, they must be
driven on the data bus pins D31–D16. The Intel486 processor expects the two low order bytes on
D15–D0. The Intel386 processor expects both the high and low order bytes on D15–D0. The
Intel386 processor always reads or writes data on the lower 16 bits of the data bus when BS16#
is asserted.
The external system must contain buffers to enable the Intel486 processor to read and write data
on the appropriate data bus pins.
sor expects data to be returned for each valid combination of byte enables and bus sizing options.
Table 4-3. Next Byte Enable Values for BS x # Cycles
Current
BE3# BE2# BE1#
1 1 1
1 1 0
1 0 0
0 0 0
1 1 0
1 0 0
0 0 0
1 0 1
0 0 1
0 1 1
NOTE: "N" means that another bus cycle is not required to satisfy the request.
4-4
Table 4-4 shows the data bus lines to which the Intel486 proces-
Next with
BE0# BE3# BE2#
0 N N
0 1 1
0 1 0
0 0 0
1 N N
1 1 0
1 0 0
1 N N
1 0 1
1 N N
BE1# BE0# BE3#
N N N
0 1 N
0 1 1
0 1 0
N N N
1 1 1
1 1 0
N N N
1 1 N
N N N
Table 4-3 shows the
Next with BS16#
BE2# BE1# BE0#
N N N
N N N
0 1 1
0 1 1
N N N
0 1 1
0 1 1
N N N
N N N
N N N