Interfacing To X86 Peripherals; Universal Peripheral Interface - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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The complete Intel387™ math coprocessor instruction set and register set have been added.
No I/O cycles are performed during floating-point instruction execution. The instruction
and data pointers are set to zero after FINIT/FSAVE. Interrupt 9 cannot occur, and interrupt
13 occurs instead.
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The Intel486 processor supports new floating-point error reporting modes to ensure DOS
compatibility. These new modes require a new bit in Control Register 0 (NE) as well as new
pins.
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Six new instructions have been added: Byte Swap (BSWAP), Exchange and Add (XADD),
Compare and Exchange (CMPXCHG), Invalidate data cache (INVD), Write-back and
Invalidate Data Cache (WBINVD) and Invalidate TLB Entry (INVLPG).
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Two new bits are defined in control register 3 for page table entries and page directory
entries.
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A new page protection feature has been added, requiring a new bit in Control Register 0.
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A new alignment check feature has been added, requiring a new bit in the flags register and
a new bit in the control register 0.
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The replacement algorithm for the translation lookaside buffer (TLB) is a pseudo least-
recently-used algorithm (PLRU), like the one used in the on-chip cache.
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Three new testability registers TR5, TR6 and TR7 have been added for testing of the on-
chip cache. TLB testability has been enhanced.
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The prefetch queue has been increased from 16 bytes to 32 bytes. A jump must always
execute after code modification to ensure proper execution of the new instruction.
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After reset, the ID in the upper byte of the DX register is 04. The contents of the base
register, including the floating-point registers, may be different after reset.
Refer to the individual Intel486 processor datasheets for more information about these features.
7.5

INTERFACING TO x86 PERIPHERALS

This section discusses the Intel486 processor interface to two peripheral devices from the x86
family: the 8041 and the 82C59A. Not all systems use these separate devices, however the exam-
ples explain in detail many of the issues surrounding slave I/O and interrupts.
7.5.1

Universal Peripheral Interface

Universal peripheral interface (UPI) devices allow customized solutions for peripheral device
control. These microcontrollers have a slave interface on-board and include an 8-bit CPU, ROM,
RAM, an I/O timer/counter and a clock. Intel supplies an EPROM implementation, which in-
cludes the 8741 and 8742 microcontrollers. The 8742 has a 2 K x 8-bit ROM and 256 K x 8-bit
RAM, an eight-bit timer/counter and 18 programmable I/O pins. It also has an 8-bit status register
and two data registers for asynchronous slave-to-master interfacing. The 8742 supports DMA, in-
terrupt and polled operations.
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