Intel Embedded Intel486 Hardware Reference Manual page 98

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
Invalidations use two pins, address hold request (AHOLD) and valid external address (EADS#).
There are two steps in an invalidation cycle. First, the external system asserts the AHOLD input
forcing the Intel486 processor to immediately relinquish its address bus. Next, the external sys-
tem asserts EADS#, indicating that a valid address is on the Intel486 processor address bus.
Figure 4-25 shows the fastest possible invalidation cycle. The Intel486 processor recognizes
AHOLD on one CLK edge and floats the address bus in response. To allow the address bus to
float and avoid contention, EADS# and the invalidation address should not be driven until the
following CLK edge. The Intel486 processor reads the address over its address lines. If the
Intel486 processor finds this address in its internal cache, the cache entry is invalidated. Note that
the Intel486 processor address bus is input/output, unlike the Intel386 processor's bus, which is
output only.
Ti
CLK
ADS#
ADDR
AHOLD
EADS#
RDY#
DATA
BREQ
†
To Processor
Figure 4-25. Fast Internal Cache Invalidation Cycle
4-34
T1 T2 Ti
†
Ti T1
†
T2 Ti
†
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