Operand Alignment - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
Table 4-6. Generating A0, A1 and BHE# from the Intel486™ Processor Byte Enables
BE3# BE2# BE1#
1 1
1 1
1 0
†
0 0
1 1
1 0
†
0 0
1 0
†
0 0
†
0 1
KEY:
†
= a non-occurring pattern of Byte Enables; either none are asserted or the pattern has byte
enables asserted for non-contiguous bytes
4.1.5

Operand Alignment

Physical 4-byte words begin at addresses that are multiples of four. It is possible to transfer a log-
ical operand that spans more than one physical 4-byte word of memory or I/O at the expense of
extra cycles. Examples are 4-byte operands beginning at addresses that are not evenly divisible
by 4, or 2-byte words split between two physical 4-byte words. These are referred to as unaligned
transfers.
Operand alignment and data bus size dictate when multiple bus cycles are required.
scribes the transfer cycles generated for all combinations of logical operand lengths, alignment,
and data bus sizing. When multiple cycles are required to transfer a multibyte logical operand,
the highest-order bytes are transferred first. For example, when the processor executes a 4-byte
unaligned read beginning at byte location 11 in the 4-byte aligned space, the three high-order
bytes are read in the first bus cycle. The low byte is read in a subsequent bus cycle.
4-10
First Cache Fill Cycle
BE0#
A0
1 0 0
0 0 0
0 0 0
0 0 0
0 1 0
0 1 0
0 1 0
1 1 0
1 1 0
1 1 0
A1 BHE# A0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 1
0 0 1
0 0 1
0 0 0
0 0 0
0 0 1
Any Other Cycle
A1 BHE#
0 1
0 0
0 0
0 0
0 0
0 0
0 0
1 1
1 0
1 0
Table 4-7 de-