Intel Embedded Intel486 Hardware Reference Manual page 61

LRU
Block
Way 0
Valid Attribute
1 Bit 3 Bits
Most programs access only a small number of pages during any short span of time. When this is
true, the pages stay in memory and the address translation information stays in the TLB. In typical
systems, the TLB satisfies 99% of the requests to access the page tables. The TLB uses a pseudo-
LRU algorithm, similar to the cache, as a content-replacement strategy.
The TLB is flushed whenever the page directory base register (CR3) is loaded. Page faults can
occur during either a page directory read or a page table read. The cache can be used to supply
data for the TLB, although this may not be desirable when external logic monitors TLB updates.
Unlike segmentation, paging is invisible to application programs and does not provide the same
kind of protection against programs altering data outside a restricted part of memory. Paging is
visible to the operating system, which uses it to satisfy application program memory require-
ments. For more information on paging and segmentation, see the Embedded Intel486™ Devel-
oper's Manual.
Valid Attribute
and Tag Block
Way 1 Way 2 Way 3
Tag Set Select
17 Bits
31
Linear Address
Figure 3-7. Translation Lookaside Buffer
INTERNAL ARCHITECTURE
Way 0 Way 1
Set 0
Set 1
Set 2
Set 3
Set 4
Set 5
Set 6
Set 7
3 Bits
15 14 12 31
Data
Block
Way 2 Way 3
Data
20 Bits
12
Physical Address
A5174-01
3-17