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Intel IntelDX4 Hardware Reference Manual

Intel IntelDX4 Hardware Reference Manual (334 pages)

Embedded Intel486 Processor

Brand: Intel | Category: Computer Hardware | Size: 3.22 MB

Table of Contents

Table of Contents

3
- Chapter 1 Guide to this Manual
  
  19
  - Manual Contents
    19
  - Special Terminology
    22
  - Electronic Support Systems
    23
    
    Faxback Service
    23
    
    World Wide Web
    23
  - Technical Support
    23
  - Product Literature
    24
    
    Related Documents
    24
- Chapter 2 Introduction
  
  27
  - Processor Features
    30
  - Intel486™ PROCESSOR PRODUCT FAMILY
    32
    
    Memory Management
    33
    
    Operating Modes and Compatibility
    33
    
    Floating-Point Unit
    34
    
    On-Chip Cache
    34
    
    Upgrade Power down Mode
    35
  - System Architecture
    35
    
    Single Processor System
    36
    
    Loosely Coupled Multi-Processor System
    37
    
    External Cache
    38
  - System Components
    35
  - Systems Applications
    39
    
    Embedded Controllers
    40
    
    Embedded Personal Computers
    40
3 Internal Architecture

43
- Chapter 3 Internal Architecture
  
  43
  - Instruction Pipelining
    50
  - Bus Interface Unit
    51
    
    Data Transfers
    52
    
    Write Buffers
    52
    
    I/O Transfers
    53
    
    Locked Cycles
    53
  - Cache Unit
    54
    
    Cache Structure
    54
    
    Cache Configuration
    56
    
    Cache Replacement
    56
    
    Cache Updating
    56
  - Instruction Prefetch Unit
    57
  - Control Unit
    58
  - Instruction Decode Unit
    58
  - Integer (Datapath) Unit
    58
  - Floating-Point Unit
    59
    
    Inteldx2™ and Inteldx4™ Processor On-Chip Floating-Point Unit
    59
  - Segmentation Unit
    59
  - 3.10 Paging Unit
    60
- Chapter 4 Bus Operation
  
  63
  - Data Transfer Mechanism
    65
    
    Memory and I/O Spaces
    65
    
    Memory and I/O Space Organization
    66
    
    Dynamic Data Bus Sizing
    67
    
    Interfacing with 8-, 16-, and 32-Bit Memories
    69
    
    Dynamic Bus Sizing During Cache Line Fills
    73
    
    Operand Alignment
    74
  - Bus Arbitration Logic
    76
  - Bus Functional Description
    79
    
    No Wait States
    80
    
    Non-Cacheable Non-Burst Single Cycle
    80
    
    Inserting Wait States
    81
    
    Multiple and Burst Cycle Bus Transfers
    81
    
    Burst Cycles
    82
    
    Non-Cacheable, Non-Burst, Multiple Cycle Transfers
    83
    
    Terminating Multiple and Burst Cycle Transfers
    83
    
    Non-Cacheable Burst Cycles
    84
    
    Cacheable Cycles
    85
    
    Byte Enables During a Cache Line Fill
    86
    
    Non-Burst Cacheable Cycles
    87
    
    Burst Cacheable Cycles
    88
    
    Effect of Changing KEN# During a Cache Line Fill
    89
    
    Adding Wait States to Burst Cycles
    90
    
    Burst Mode Details
    90
    
    Burst and Cache Line Fill Order
    91
    
    Interrupted Burst Cycles
    92
    
    8- and 16-Bit Cycles
    93
    
    Locked Cycles
    95
    
    Pseudo-Locked Cycles
    96
    
    Floating-Point Read and Write Cycles
    97
    
    Invalidate Cycles
    97
    
    Rate of Invalidate Cycles
    99
    
    Running Invalidate Cycles Concurrently with Line Fills
    99
    
    Bus Hold
    102
    
    4.3.10 Interrupt Acknowledge
    104
    
    4.3.11 Special Bus Cycles
    105
    
    HALT Indication Cycle
    105
    
    Shutdown Indication Cycle
    105
    
    Stop Grant Indication Cycle
    105
    
    4.3.12 Bus Cycle Restart
    107
    
    4.3.13 Bus States
    109
    
    Floating-Point Error Handling for the Inteldx2™ and Inteldx4™ Processors
    110
    
    Floating-Point Exceptions
    110
    
    Inteldx2™ and Inteldx4™ Processors Floating-Point Error Handling in AT-Compatible Systems
    111
  - Enhanced Bus Mode Operation (Write-Back Mode)
    114
    
    Burst Cycles
    114
    
    Summary of Bus Differences
    114
    
    Burst Cycle Signal Protocol
    115
    
    Non-Cacheable Burst Operation
    115
    
    Cache Consistency Cycles
    116
    
    Snoop Collision with a Current Cache Line Operation
    118
    
    Snoop under AHOLD
    118
    
    Snoop During Replacement Write-Back
    123
    
    Snoop under BOFF
    125
    
    Snoop under HOLD
    128
    
    Snoop under HOLD During Replacement Write-Back
    130
    
    Locked Cycles
    131
    
    Snoop/Lock Collision
    132
    
    Flush Operation
    133
    
    Pseudo Locked Cycles
    134
    
    Snoop under AHOLD During Pseudo-Locked Cycles
    134
    
    Snoop under Hold During Pseudo-Locked Cycles
    135
    
    Snoop under BOFF# Overlaying a Pseudo-Locked Cycle
    136
- Chapter 5 Memory Subsystem Design
  
  139
  - Introduction
    141
  - Processor and Cache Feature Overview
    141
    
    The Burst Cycle
    141
    
    The KEN# Input
    142
    
    Bus Characteristics
    144
    
    Improving Write Cycle Latency
    145
    
    Interleaving
    145
    
    Write Posting
    145
    
    Second-Level Cache
    146
6 Cache Subsystem

149
- Chapter 6 Cache Subsystem
  
  149
  - Cache Memory
    151
    
    What Is a Cache
    151
    
    Why Add an External Cache
    152
  - Introduction
    151
  - Cache Trade-Offs
    152
    
    Cache Size and Performance
    153
    
    Associativity and Performance Issues
    155
    
    Block/Line Size
    160
    
    Replacement Policy
    161
  - Updating Main Memory
    161
    
    Write-Through and Buffered Write-Through Systems
    162
    
    Cache Consistency
    163
    
    Write-Back System
    163
  - Non-Cacheable Memory Locations
    165
  - Cache and Dma Operations
    166
  - Cache for Single Versus Multiple Processor Systems
    166
    
    Cache in Multiple Processor Systems
    166
    
    Cache in Single Processor Systems
    166
  - AN Intel486™ PROCESSOR SYSTEM EXAMPLE
    168
    
    The Memory Hierarchy and Advantages of a Second-Level Cache
    169
7 Peripheral Subsystem

171
- Chapter 7 Peripheral/Processor Bus Interface
  
  173
  - Mapping Techniques
    173
  - Dynamic Bus Sizing
    175
  - Address Decoding for I/O Devices
    177
    
    Address Bus Interface
    178
    
    8-Bit I/O Interface
    179
    
    16-Bit I/O Interface
    182
    
    32-Bit I/O Interface
    186
  - Basic Peripheral Subsystem
    189
    
    Bus Control and Ready Logic
    192
    
    Bus Control Signal Description
    193
    
    Processor Interface
    193
    
    Wait State Generation Signals
    194
    
    Wait State Generator Logic
    194
    
    Address Decoder
    195
    
    Data Transceivers
    198
    
    Recovery and Bus Contention
    198
    
    Non-Cacheability of Memory-Mapped I/O Devices
    199
    
    Write Buffers and I/O Cycles
    199
    
    Write Buffers and Recovery Time
    199
    
    Intel486™ Processor On-Chip Cache Consistency
    200
  - I/O Cycles
    201
    
    Read Cycle Timing
    201
    
    Write Cycle Timings
    203
  - DIFFERENCE between the Intel486 DX PROCESSOR FAMILY and Intel386 PROCESSORS
    205
  - INTERFACING to X86 PERIPHERALS
    206
    
    Universal Peripheral Interface
    206
    
    82C59A Interface
    207
    
    Single Interrupt Controller
    207
    
    Cascaded Interrupt Controllers
    209
    
    Handling more than 64 Interrupts
    210
  - Intel486™ PROCESSOR LAN CONTROLLER INTERFACE
    210
    
    82596CA Coprocessor
    210
    
    Hardware Interface
    213
    
    Processor and Coprocessor Interaction
    216
    
    Media Access
    218
    
    Memory Structure
    218
    
    Bus Throttle Timers
    219
    
    Transmit and Receive Operation
    219
    
    Design Considerations
    220
    
    82596 Co-Processor Performance
    221
    
    82557 High Speed LAN Controller Interface
    222
    
    82557 Overview
    222
    
    Features and Enhancements
    223
    
    82557 Bus Operations
    224
    
    Initializing the 82557
    224
    
    PCI Bus Interface
    224
    
    Controlling the 82557
    225
8 System Bus Design

227
- Chapter 8
  
  229
  - Introduction
    229
  - System Bus Interface
    229
  - Eisa Bus: System Design Example
    230
    
    Introduction to the EISA Architecture
    230
    
    An Example EISA Chip Set
    231
    
    Clock, Control and Status Interface
    237
    
    EBC Host Bus Interface
    237
    
    Host Bus Acquisition and Release
    238
    
    Host Local Memory and I/O Interface
    238
    
    Lock, Snoop, and Address Greater than 16 Mbytes
    238
    
    EBC and EISA Bus Interface Signals
    239
    
    EISA/ISA Bus Interface to the EBC
    239
    
    EBC and ISA Bus Interface Signals
    240
    
    EBC and ISP Interface
    241
    
    EBC and EBB Data and Address Buffer Controls
    242
    
    Functions of the ISP
    244
    
    ISP-To-EISA Interface
    245
    
    ISP-To-Host Interface
    245
  - Pci Bus: System Design Example
    247
    
    Example PCI System Design
    247
    
    Introduction to PCI Architecture
    247
    
    Control and Status Interface
    252
    
    Host Bus Slave Device
    252
    
    Host CPU Interface
    252
    
    L1 Cache Support
    252
    
    PCI Bus Cycles Support
    254
    
    Exclusive Cycles
    255
    
    Host to PCI Cycles
    255
    
    Status and Control Interface
    256
    
    Status and Control Interface
    257
    
    System Controller/Isa Bridge Link Interface
    257
    
    Data Byte Swapping (ISA Master or DMA to ISA Device)
    258
    
    I/O Recovery Support
    258
    
    ISA Interface
    258
    
    SYSCLK Generation
    258
    
    Wait-State Generation
    259
9 Performance

263
- Performance Considerations
  263
- Introduction
  265
- Instruction Execution Performance
  266
- Internal Cache Performance Issues
  268
- On-Chip Write Buffers
  271
- External Memory Considerations
  272
- Second-Level Cache Performance Considerations
  275
- Dram Design Techniques
  278
- Extended Data Output RAM (EDO RAM)
  278
- Floating-Point Performance
  280
10 Physical Design and

283

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