Rate Of Invalidate Cycles; Running Invalidate Cycles Concurrently With Line Fills - Intel Embedded Intel486 Hardware Reference Manual

Ti
CLK
ADS#
ADDR
AHOLD
EADS#
RDY#
DATA
BREQ
†
To Processor
Figure 4-26. Typical Internal Cache Invalidation Cycle
4.3.8.1

Rate of Invalidate Cycles

The Intel486 processor can accept one invalidate per clock except in the last clock of a line fill.
One invalidate per clock is possible as long as EADS# is deasserted in ONE or BOTH of the fol-
lowing cases:
1. In the clock in which RDY# or BRDY# is asserted for the last time.
2. In the clock following the clock in which RDY# or BRDY# is asserted for the last time.
This definition allows two system designs. Simple designs can restrict invalidates to one every
other clock. The simple design need not track bus activity. Alternatively, systems can request one
invalidate per clock provided that the bus is monitored.
4.3.8.2

Running Invalidate Cycles Concurrently with Line Fills

Precautions are necessary to avoid caching stale data in the Intel486 processor cache in a system
with a second-level cache. An example of a system with a second-level cache is shown in
Figure 4-27.
An external device can write to main memory over the system bus while the Intel486 processor
is retrieving data from the second-level cache. The Intel486 processor must invalidate a line in its
internal cache if the external device is writing to a main memory address that is also contained in
the Intel486 processor cache.
T1 T2 Ti
†
BUS OPERATION
Ti T1 T1
†
T2
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