Intel Embedded Intel486 Hardware Reference Manual page 55

Valid/LRU
Block
Way 0
LRU Valid
X 1 X X
line is valid
31
†
20 bits for the IntelDX4™ processor
Cache addressing is performed by dividing the high-order 28 bits of the physical address into
three parts, as shown in
128, within the cache. The high-order 21 bits (20 on the IntelDX4 processor) are the tag field;
these bits are compared with tags for each cache line in the indexed set, and they indicate whether
a 16-byte cache line is stored for that physical address. The low-order 4 bits of the physical ad-
dress select the byte within the cache line. Finally, a 4-bit valid field, one for each way within a
given set, indicates whether the cached data at that physical address is currently valid.
Tag
Block
Way 1 Way 2 Way 3
†
Tag - 21 bits
Match
11
Tag Field
Physical Address
Figure 3-5. Cache Organization
Figure 3-5. The 7 bits of the index field specify the set number, one of
INTERNAL ARCHITECTURE
Way 0 Way 1
Set 0
Set 1
Set 2
Set N
Set 126
Set 127
Selects
Index
byte
is N
4 0
Index Field xxxx
Data
Block
Way 2 Way 3
Data - 16 bytes
A5141-02
3-11