Cache Unit; Cache Unit; Cache Structure - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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Writes — Single I/O writes are never buffered. When processing an OUT instruction,
internal execution stops until all buffered writes and the I/O write are completed on the
processor bus. This allows time for external logic to drive a cache invalidate cycle or mask
interrupts before the processor executes the next instruction. The processor completes
updating all memory locations before writing to the I/O location. Repeated OUT
instructions may be buffered.
The write buffers and the cache unit determine I/O device recovery time. In the Intel386 proces-
sor, back-to-back write recovery time could be guaranteed to exceed a certain value by inserting
a jump to the next instruction that writes to the I/O device. This forced an instruction prefetch
cycle that could only be performed after the preceding write was completed. This technique is not
used in the Intel486 processor because a prefetch can be satisfied internally by the cache and re-
covery time may be too short. The same effect is achieved in the Intel486 processor by explicitly
generating a read to an area of memory that is not cacheable. Because the Intel486 processor does
not buffer single I/O writes, such a read is not done until the I/O write is completed.
3.3

CACHE UNIT

The cache unit stores copies of recently read instructions, operands, and other data. When the pro-
cessor requests information already in the cache, called a cache hit, no processor-bus cycle is re-
quired. When the processor requests information not in the cache, called a cache miss, the
information is read into the cache in one or more 16-byte cacheable data transfers, called cache
line fills. An internal write request to an area currently in the cache causes two distinct actions if
the cache is using a write-through policy: the cache is updated, and the write is also passed
through the cache to memory. If the cache is using a write-back policy, then the internal write
request only causes the cache to be updated and the write is stored for future main memory up-
dating.
The cache transfers data to other units on two 32-bit buses, as shown in
receives linear addresses on a 32-bit bus and the corresponding physical addresses on a 20-bit
bus. The cache and instruction prefetch units are closely coupled. 16-Byte blocks of instructions
in the cache can be passed quickly to the instruction prefetch unit. Both units read information in
16-byte blocks.
The cache can be accessed as often as once each clock. The cache acts on physical addresses,
which minimizes the number of times the cache must be flushed. When both the cache and the
cache write-through functions are disabled, the cache may be used as a high-speed RAM.
3.3.1

Cache Structure

The cache has a four-way set associative organization. There are four possible cache locations to
store data from a given area of memory. Four-way association is a compromise between the speed
of a direct-mapped cache during cache hits and the high cache-hit ratio of a fully associative
cache. As shown in Figure
taining 128 16-byte sets, or cache lines (the DX4 processor has 256 16-byte sets). Each cache line
holds data from 16 successive byte addresses in memory, beginning with an address divisible
by 16.
3-10
3-5, the 8-Kbyte data block is divided into four data ways, each con-
Figure 3-1. The cache