EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
1
2
CLK
HOLD
HLDA
EADS#
INV
HITM#
Prefetch Cycle
A31–A4
A3–A2
0
ADS#
BLAST#
CACHE#
RDY#
BRDY#
W/R#
†
To Processor
Figure 4-45. Snoop using HOLD during a Non-Cacheable, Non-Burstable Code Prefetch
4.4.3.6
Snoop under HOLD during Replacement Write-Back
Collision of snoop cycles under a HOLD during the replacement write-back cycle can never oc-
cur, because HLDA is asserted only after the replacement write-back cycle (burst or non-burst)
is completed.
4-66
3
4
5
6
7
8
4
8
9
10
11
12
13
14
†
Write Back Cycle
0
15
16
17
18
19
Prefetch
Cont.
4
8
C
C
242202-157
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