Intel Embedded Intel486 Hardware Reference Manual page 260

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
8.4.5.6 Status and Control Interface
Bus Address Latch Enable, BALE, is asserted by the ISA bridge to indicate that the address
(SA19–SA0, LA23–LA17) and SBHE# signal lines are valid. This signal is deasserted after a
hard reset.
Address Enable, AEN, is asserted during DMA cycles to present I/O slaves from misinterpreting
DMA cycles as valid I/O cycles. This signal is also asserted during ISA bridge-initiated refresh
cycles. This signal is deasserted after a hard reset.
I/O Channel Ready, IOCHRDY, is deasserted by resources on the ISA bus to indicate that addi-
tional time (wait-states) is required to complete the cycle. This signal is normally high on the ISA
bus. IOCHRDY is an input when the ISA bridge owns the ISA bus and the CPU or a PCI agent
is accessing an ISA slave, or during DMA transfers. IOCHRDY is output when an external ISA
bus master owns the ISA bus and is accessing main memory or an ISA bridge register. As an ISA
bridge output, IOCHRDY is deasserted from the falling edge of the ISA commands. After data is
available for an ISA master read or the ISA bridge latches the data for a write cycle, IOCHRDY
is asserted for 70 ns. After 70 ns, the ISA bridge three-states IOCHRDY. The ISA bridge does
not drive this signal when an ISA bus master is accessing an ISA bus slave. IOCHRDY is 3-stated
upon CPURST.
16-bit I/O Chip Select, ISCS16#, is driven by I/O devices on the ISA bus to indicate that they
support 16-bit I/O bus cycles.
I/O Channel Check, IOCHK#, can be driven by any resource on the ISA bus. When asserted, it
indicates that a parity or an uncorrectable error has occurred for a device or memory on the ISA
bus. If IOCHK# is asserted and NMIs are enabled, an NMI is generated to the CPU.
I/O Read, IOR#, when asserted indicates to an ISA I/O slave device that the slave may drive data
on the ISA data bus (SD15–SD0). The I/O slave device must hold the data valid until after IOR#
is deasserted. IOR# is an output when the ISA bridge owns the ISA bus. IOR# is an input when
an external ISA master owns the ISA bus. This signal is deasserted after a hard reset.
I/O Write, IOW#, asserted indicates to an ISA I/O slave device that the slave may latch data from
the ISA data bus (SD15–SD0). IOW# is an output when the ISA bridge owns the ISA bus. IOW#
is an input when an external ISA master owns the ISA bus. This signal is deasserted after a hard
reset.
Unlatched Address, LA23–LA17, are bi-directional address lines allowing accesses to physical
memory on the ISA bus up to 16 Mbytes. LA23–LA17 are outputs when the ISA bridge owns the
ISA bus. The LA23–LA17 lines become inputs when an ISA master owns the ISA bus. The
LA23–LA17 signals are driven to an unknown state after a hard reset.
System Address bus, SA19–SA0, are outputs when the ISA bridge owns the ISA bus. SA19–SA0
are inputs when an external ISA master owns the ISA bus. Note that SA19–SA17 have the same
values as LA19–LA17 for all memory cycles. For I/O accesses only SA15–SA0 are used. SA19–
SA0 are driven to an unknown state after a hard reset.
System Byte High Enable, SBHE#, indicates, when asserted, that a byte is being transferred on
the upper byte (SD15–SD8) of the data bus. SBHE# is deasserted during refresh cycles. SBHE#
is an output when the ISA bridge owns the ISA bus and an input when an external ISA master
owns the ISA bus. This signal is at an unknown state after a hard reset.
8-32