Table of Contents
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P
3-16
Page tables,
3-5
3-16
Paging unit,
,
2-5
Paging, overview,
10-19
Parallel termination,
PC/AT address, defined,
PCI
example of system design,
interface to the 82557,
overview of architecture,
Peripheral subsystem, components of,
Personal computers, embedded,
Posted write
7-32
circuit timings,
9-15
cycles,
10-1
Power dissipation,
Power management features,
Processor bus
4-16
basic 2-2 cycle,
4-17
basic 3-3 cycle,
4-17
burst cycles,
4-21
cacheable cycles,
5-1
features,
4-43
restart cycles,
6-14
snooping,
2-4
Product family,
10-29
Propagation delay,
2-5
3-6
Protected mode,
,
4-70
Pseudo locked cycles,
3-12
Pseudo-LRU,
R
Read cycles
7-29
7-30
timing,
to
2-5
3-6
Real mode,
,
10-14
Reflection voltage,
Registers
4-22
4-46
CR0,
,
3-17
CR3,
10-39
10-41
debug,
to
3-14
general purpose,
3-12
4-47
machine status,
,
notational conventions,
1-6
Related documents,
4-43
Restart cycles,
1-4
8-19
8-34
to
7-52
8-19
7-17
2-12
2-1
4-73
to
1-4
S
2-10
Second-level cache,
6-19
memory hierarchy,
6-16
6-18
overview,
to
see also Cache
6-9
Sector buffering cache,
3-5
Segmentation unit,
,
Segmentation, overview,
10-18
Series termination,
6-8
Set associative cache,
1-4
Set, defined,
Shutdown indication cycle,
Signals
82596CA coprocessor,
3-8
4-1
address,
,
7-21
7-22
bus control,
to
4-1
byte enables,
Cache Enable (KEN#),
5-2
KEN#,
notational conventions,
2-3
SMI#,
2-7
UP#,
7-22
wait state generation,
Single processor system,
2-1
2-3
SL technology,
,
4-52
4-73
Snoop cycles,
to
10-32
Star connection,
4-42
Stop grant bus cycle,
10-11
Strip lines,
6-9
Sub-block cache,
System architecture overview,
System Management Mode,
T
1-5
Technical support,
1-4
Terminology,
Thermal characteristics,
Thevenins equivalent circuit,
Translation lookaside buffer (TLB),
Transmission lines
10-13
loaded,
10-10
micro strip,
10-11
strip,
INDEX
5-6
,
3-15
2-5
4-41
7-42
5-2
1-4
2-8
2-9
to
6-14
,
2-7
2-8
to
3-6
10-33
10-20
3-16
3-17
to
Index-5
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