Wait State Generation Signals; Wait State Generator Logic - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
IOR#—The I/O Read Signal. This signal is active low and is generated when the Intel486 pro-
cessor's W/R# output signal is low, indicating a read cycle. When IOR# is low, data can be read
from the peripheral device. The signal is deasserted with the rising edge of the RDY# signal.
IOW#—Interrupt Write Signal. This signal is generated by the controller logic and is active
low when W/R# status signal from the Intel486 processor is high, indicating that the processor
will write to the I/O device which has its present address on the address bus. When IOW# is low,
data from the Intel486 processor can be written to the peripheral device. The signal is valid until
the rising edge of the RDY# signal.
INTA—Interrupt Acknowledge Signal. This signal is active high and is generated to acknowl-
edge an interrupt from peripheral devices such as 82C59A, etc. The signal function is discussed
in Section 7.5, "Interfacing to x86 Peripherals."
7.2.2.2

Wait State Generation Signals

SEL0, SEL1, SEL2. These programmable wait state select inputs can be controlled by DIP
switches or can be programmed by the processor. In the control logic example, a seven-state wait
state generator is implemented. The purpose and functionality of a wait state generator is de-
scribed in the next section.
C0, C1, C2—Counter Outputs 0, 1, and 2. These outputs are internally decoded to generate a
RDY# signal and they represent the number of wait states implemented by the bus control logic.
The wait state generation logic is used to patch timing differences between the peripheral device
and the Intel486 processor. The next section discusses this issue in detail.
7.2.3

Wait State Generator Logic

When the memory subsystem or the I/O device cannot respond to the processor in time, wait
states are added to the bus cycles. During wait states the processor freezes the state of the bus. On
the Intel486 processor, wait states are activated by the RDY# signal (when asserted). Additional
wait states are generated as long as RDY# stays deasserted, and the processor resumes its opera-
tions once RDY# is asserted.
Timing differences between microprocessors and peripheral devices are common, but can be
compensated for by using wait states or some other delay techniques. The following major timing
parameters must be accounted for:
1. Minimum pulse width for read and write timings
2. Chip select access time
3. Address access time
4. Access time from read strobe
It is possible to adjust the minimum pulse width and chip select access time by adding wait states.
Refer to Section CHAPTER 4, "Bus Operation"
states to basic bus cycles.
7-22
for more detailed information on adding wait