Table of Contents
Advertisement
PERIPHERAL SUBSYSTEM
The 32-bit Intel486 processor requires 32-bit-to-8-bit byte-steering logic to interface to an 8-bit
UPI device.
7.5.2
82C59A Interface
The following discussion of interrupt-driven processor environments is a helpful preface to the
section on interfacing Intel486 processor systems to the 82C59A programmable interrupt control-
ler. It also provides a context to review other interrupt controller implementations.
In a microcomputer system, the CPU must efficiently service I/O devices such as keyboards and
display monitors to minimize overhead. One technique is polling, in which the processor tests
each device in sequence to determine whether servicing is needed. A large portion of the main
program must be devoted to polling, at a cost of system throughput.
Interrupts provide a more efficient and desirable alternative for servicing I/O devices. Using in-
terrupts, a hardware signal can cause the main program to change its execution path. These inter-
rupts are acknowledged only between instructions—with the exception of the bus error signal.
The Intel486 processor reacts to interrupts by saving the program address and then performing
special interrupt processing (as explained in the Embedded Intel486™ Processor Family Devel-
oper's Manual). Once the current program address and flags are saved on a stack, the Intel486
processor receives an eight-bit vector identifying an entry in the interrupt table that contains the
starting address of the interrupt service routine. The vector interrupt allows a hardware mecha-
nism to select a separate service routine for each interrupt source. Once the interrupt service rou-
tine is executed, the previous processor state is restored, and program execution resumes. The
Intel486 processor can handle up to 256 interrupts/exceptions. Refer to the Embedded Intel486™
Processor Family Developer's Manual for the interrupt table.
The interrupt-driven environment increases system throughput and allows more tasks to be ac-
complished by the processor, thus increasing overall cost-effectiveness.
The 82C59A is a high performance CMOS programmable interrupt controller which manages the
interrupt-driven Intel486 processor system environment. It accepts requests from peripheral de-
vices and determines device priorities. The 82C59A provides the processor with an eight-bit vec-
tor interrupt. The interrupt points to an address in the vector table, and the processor's INTA#
signal (generated by the bus controller logic) enables the vector data on the data bus.
Individual 82C59A devices can be cascaded to accommodate up to 64 interrupts. Later sections
discuss how to implement such configurations.
7.5.2.1
Single Interrupt Controller
Figure 7-19
shows a basic I/O interface between the Intel486 processor and a single 82C59A de-
vice. The address decoder generates the chip select (CS#) signal, while the bus control ready logic
generates the interrupt acknowledge (INTA#), write (WR#) and read (RD#) signals. In this ex-
ample, the 82C59A is used in the master mode since the SP/EN# pin is high. The A0 address pin
is used to decipher various processor command words and to determine the status that the proces-
sor wishes to read. The A0 pin is connected to the processor's A2 pin and is also used to distin-
guish between two consecutive interrupt acknowledge cycles. The 82C59A register address must
therefore be located at two consecutive doubleword boundaries.
7-35
Advertisement
Chapters
Table of Contents
