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1
2
CLK
HOLD
HLDA
EADS#
INV
HITM#
A31–A4
A3–A2
0
ADS#
BLAST#
CACHE#
BRDY#
W/R#
†
To Processor
If HOLD is asserted during a non-cacheable, non-burst code prefetch cycle, as shown in
Figure
4-45, the Write-Back Enhanced IntelDX4 processor issues HLDA in clock seven (which
is the clock period in which the next RDY# is asserted). If the system snoop hits a modified line,
the snoop write-back cycle begins after HOLD is released. After the snoop write-back cycle is
completed, an ADS# is issued and the code prefetch cycle resumes.
3
4
5
6
7
8
†
Linefill
4
8
C
Figure 4-44. Snoop under HOLD during Line Fill
9
10
11
12
13
14
0
4
BUS OPERATION
15
16
17
18
19
8
C
242202-156
4-65
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