External Memory Considerations - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
9.5

EXTERNAL MEMORY CONSIDERATIONS

9.5.1 Introduction
A well-designed external memory system is needed to optimize Intel486 processor system per-
formance. A system can be designed using different combinations of SRAMs and DRAMs to pro-
vide different price/performance levels. SRAMs have faster access times and do not require
precharging between accesses or refresh cycles. DRAMs offer higher densities and are less ex-
pensive, but they require refresh circuitry, and require the addition of wait states due to the longer
access times.
The overall performance of a microprocessor system is directly related to the performance of the
memory subsystem. The great majority of bus cycles are used to access memory for instructions
and data. As processor speeds increase, so does the demand for higher-speed memories because
a high-performance processor that is coupled with a low performance memory offers no better
throughput than a low-performance processor.
The cost of using only fast memories in a system may be prohibitive. Yet as slower devices are
added to lower the overall cost, the performance penalty of added wait states increases. At fre-
quencies of 25 MHz or more, optimum memory performance can only be achieved by using very
fast memory devices.
The cost performance trade-off can be compromised by partitioning functions and using a com-
bination of both fast and slow memories. The most frequently used functions are placed in a faster
memory. A common use of faster memory devices is implementation of an external cache, built
of fast SRAM devices.
Fast SRAM devices have high enough bandwidth to achieve optimum performance. An external
cache (also called L2 cache) can also be used for higher performance. Chapter 6 covers L2 cache
concepts.
Regardless of the use of an external cache, the external memory system consists of a combination
of EPROM and DRAM devices. EPROM devices tend to have a long access time. Being nonvol-
atile, EPROMs are used primarily for initialization routines. After initialization EPROMs are ac-
cessed infrequently. Thus, system performance is not dependent upon EPROM latency. If a high-
level of performance is desired, EPROM contents may be copied to the DRAM memory array.
This technique is called shadowing.
Organization of the DRAM memory array is more critical to system performance. DRAM opti-
mization techniques can be used to reduce the average latency of accesses to DRAM devices.
Several of the memory design concepts described in this chapter depend on the principle of lo-
cality for high performance. The locality principle basically states that when a program referenc-
es a particular location in memory, there is a high probability that nearby locations will then also
be referenced. Caches and paged memory DRAM design techniques offer high performance be-
cause of locality.
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