Dynamic Bus Sizing - Intel Embedded Intel486 Hardware Reference Manual

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Memory mapping offers more flexibility in Protected Mode than I/O mapping. Memory-
mapped devices are protected by the memory management and protection features. A
device can be inaccessible to a task, visible but protected, or fully accessible, depending on
where it is mapped. Paging and segmentation provide the same protection levels for 4-
Kbyte pages or variable length segments, which can be swapped to the disk or shared
between programs. The Intel486 processor supports pages and segments to provide the
designer with maximum flexibility.
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The I/O privilege level of the Intel486 processor protects I/O-mapped devices by either
preventing a task from accessing any I/O devices or by allowing a task to access all I/O
devices. A virtual-8086 mode I/O permission bitmap can be used to select the privilege
level for a combination of I/O bytes.
7.1.2

Dynamic Bus Sizing

Dynamic data bus sizing allows a direct processor connection to 32-, 16- or 8-bit buses for mem-
ory or I/O devices. The Intel486 processors support dynamic data bus sizing, except for the Ultra-
Low Power Intel486 GX processor, which has a 16-bit data bus only. With dynamic bus sizing,
the bus width is determined during each bus cycle to accommodate data transfers to or from 32-
bit, 16-bit or 8-bit devices. The decoding circuitry can assert BS16# for 16-bit devices, or BS8#
for 8-bit devices for each bus cycle. For addressing 32-bit devices, both BS16# and BS8# are
deasserted. If both BS16# and BS8# are asserted, an 8-bit bus width is assumed.
Appropriate selection of BS16# and BS8# drives the Intel486 processor to run additional bus cy-
cles to complete requests larger than 16-bits or 8-bits. When BS16# is asserted, a 32-bit transfer
is converted into two 16-bit transfers (or three transfers if the data is misaligned). Similarly, as-
serting BS8# converts 32-bit transfers into four 8-bit transfers. The extra cycles forced by the
BS16# or BS8# signals should be viewed as independent cycles. BS16# or BS8# are normally
driven active during the independent cycles. The only exception is when the addressed device can
vary the number of bytes that it can return between the cycles.
The Intel486 processor drives the appropriate byte enables during the independent cycles initiat-
ed by BS8# and BS16#. Addresses A31–A2 do not change if accesses are to a 32-bit aligned area.
Table 7-1 shows the set of byte enables that is generated on the next cycle for each of the valid
possibilities of the byte enables on the current cycle. BEx# must be ignored for 16-byte cycles to
memory-mapped devices.
PERIPHERAL SUBSYSTEM
7-3