Intel Embedded Intel486 Hardware Reference Manual page 78

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
Figure 4-9 shows more than one primary bus master and two secondary masters, and the arbitra-
tion logic is more complex. The arbitration logic resolves bus contention by ensuring that all de-
vice requests are serviced one at a time using either a fixed or a rotating scheme. The arbitration
logic then passes information to the Intel486 processor, which ultimately releases the bus. The
arbitration logic receives bus control status information via the HOLD and HLDA signals and re-
lays it to the requesting devices.
HLDA 0
HOLD 0
Intel486™
Processor
Figure 4-9. Single Intel486™ Processor with Multiple Secondary Masters
As systems become more complex and include multiple bus masters, hardware must be added to
arbitrate and assign the management of bus time to each master. The second master may be a
DMA controller that requires bus time to perform memory transfers or it may be a second pro-
cessor that requires the bus to perform memory or I/O cycles. Any of these devices may act as a
bus master. The arbitration logic must assign only one bus master at a time so that there is no con-
tention between devices when accessing main memory.
4-14
BREQ BDCK
Arbitration
Logic
ACQ
I/O
ACK
DMA
MEM
DRQ
DACK
Address Bus
Data Bus
Control Bus