Table of Contents
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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
Intel486 processor
10-37
debugging,
differences with Intel386
7-33
7-34
processor,
to
9-2
execution times,
2-2
2-3
features,
to
3-1
functional units,
9-3
instruction mix,
interfacing to 8042 devices,
overview of embedded processors,
2-4
product options,
thermal characteristics,
10-25
Interference,
10-25
electromagnetic,
10-28
electrostatic,
9-14
Interleaving,
Internal cache
see Level-1 cache or Cache,
Interrupt acknowledge cycles,
Interrupt controllers
7-35
7-36
82C59A,
to
7-37
7-38
cascaded,
to
7-35
single,
Interrupts
handling more than 64,
4-33
Invalidate cycles,
to
ISA bus, interface signals with EBC,
ISP
8-16
functions of,
interface to EISA system bus,
8-17
interface to host,
8-13
interface wit EBC,
K
5-2
KEN#,
L
L2 cache
see Second-level cache
LAN controller
7-38
82596CA,
7-32
Latches,
10-30
Latch-up,
10-16
Lattice diagram,
Leaded capacitors, decoupling,
Index-4
7-34
2-1
10-33
6-19
4-40
7-38
4-37
8-12
8-17
10-9
Level-1 cache
see also Cache
6-3
hit rates,
6-10
Line size, in cache,
1-6
Literature,
1-6
Literature, ordering,
3-9
4-31
Locked cycles,
,
Loosely coupled multiprocessor system,
LRU cache replacement,
M
Machine status register,
1-1
Manual contents,
Measurements, defined,
Media access through 82596CA
7-46
coprocessor,
Memory
4-3
16-bit,
4-3
8-bit,
9-8
external,
4-2
I/O space and,
2-5
management,
7-1
mapping techniques,
6-15
non-cacheable,
9-1
9-8
performance,
,
6-11
updating from cache,
Memory management unit,
10-10
Micro strip lines,
4-14
Multiple bus masters,
2-9
Multiprocessor system,
N
Non-cacheable memory,
Notational conventions,
O
2-6
On-chip cache,
see also Cache
9-5
performance,
On-chip floating-point unit,
2-5
Operating modes,
Overlapping write cycles,
10-13
Overshoot,
1-7
,
2-9
3-12
3-12
4-47
,
1-3
3-5
6-15
1-3
3-15
5-5
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