Pci Bus: System Design Example; Pci Bus: System Design Example; Introduction To Pci Architecture; Example Pci System Design - Intel Embedded Intel486 Hardware Reference Manual

8.4

PCI BUS: SYSTEM DESIGN EXAMPLE

8.4.1

Introduction to PCI Architecture

The PCI (Peripheral Component Interconnect) bus is the descendant of the VESA VL bus and is
a widely-implemented embedded system solution. The PCI standard was defined by Intel to en-
courage designers to adopt a common system bus architecture that would accommodate future
computing needs. Because the VESA VL standard does not take a sufficient long-term approach,
the PCI standard does not support VESA VL. The PCI standard provides the following features.
•
32-bit or 64-bit address buses to accommodate 32-bit and 64-bit CPUs and bus masters
•
32-bit or 64-bit data transfers
•
33 MHz and 66 MHz PCI bus operation speeds
•
132 Mbytes/sec transfer rate for 33 MHz/32-bit implementation, 264 Mbytes/sec for
66 MHz/32-bit or 33 MHz/64-bit implementations, and 524 Mbytes/s for 66 MHz/64-bit
implementation.
•
All read and write transfers over the PCI bus are burst transfers.
The PCI bus handles 32-bit wide address and data buses in the 32-bit implementation. The PCI
specification also provides for 64-bit wide address and data buses (address and data buses by PCI
standards are muxed).
All actions on the PCI bus are synchronized using the PCICLK signal. Revision 1.0 of the spec-
ification requires that all devices support 16-33 MHz operation. Revision 2.1 requires that all de-
vices support operation down to 0 MHz. Revision 2.2 adds support for 66 MHz implementation,
requiring that all devices operate from 0 MHz-66 MHz.
PCI-based computers support a Bus Initiator/Target architecture for intelligent peripherals. All
transactions on the PCI bus are in burst mode. The initiator starts by driving an address on the
PCI Address/Data bus and by driving the command type onto the PCI Command/Byte Enable
bus. Each PCI target latches the address and decodes the start address and command type to de-
termine if it is the addressed device. The device also determines the type of transaction in
progress. Upon completion of the address phase, the PCI Address/Data bus is used to transfer da-
ta. The target must latch the start address and increment the address to point to the next address
for each subsequent data transfer.
PCI systems provide a centralized arbiter that allows efficient bus sharing between multiple PCI
bus initiators. Although the PCI specification does not specify the exact method of arbitration
(such as fixed and rotational), the 2.1 specification states that the arbiter is required to implement
a fairness algorithm to avoid deadlocks. Fairness means that each potential bus master must be
granted access to the bus independent of other requests. However, this does not mean that all
agents are required to have equal access to the bus.
8.4.2

Example PCI System Design

This section describes an example of the PCI architecture implemented in an embedded Intel486
processor system.
SYSTEM BUS DESIGN
8-19