Processor Features - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
Intel486 processors are available in a full range of speeds (16 MHz to 100 MHz), packages (PGA,
SQFP, PQFP, TQFP), and voltages (5 V, 3.3 V, 3.0 V and 2.0 V) to meet many system design
requirements.
2.1

PROCESSOR FEATURES

All Intel486 processors consist of a 32-bit integer processing unit, an on-chip cache, and a mem-
ory management unit. These ensure full binary compatibility with the 8086, 8088, 80186, 80286,
Intel386™ SX, and Intel386 DX processors, and with all versions of Intel486 processors. All
Intel486 processors offer the following features:
• 32-bit RISC integer core — The Intel486 processor performs a complete set of arithmetic
and logical operations on 8-, 16-, and 32-bit data types using a full-width ALU and eight
general purpose registers.
• Single Cycle Execution — Many instructions execute in a single clock cycle.
• Instruction Pipelining — The fetching, decoding, address translation, and execution of
instructions are overlapped within the Intel486 processor.
• On-Chip Floating-Point Unit — The IntelDX2 and Intel DX4 processors support the 32-,
64-, and 80-bit formats specified in IEEE standard 754. The unit is binary compatible with
the 8087, Intel287, and Intel387 coprocessors, and with the Intel OverDrive
• On-Chip Cache with Cache Consistency Support — An 8-Kbyte (16-Kbyte on the IntelDX4
processor) internal cache is used for both data and instructions. Cache hits provide zero wait
state access times for data within the cache. Bus activity is tracked to detect alterations in
the memory represented by the internal cache. The internal cache can be invalidated or
flushed so that an external cache controller can maintain cache consistency.
• External Cache Control — Write-back and flush controls for an external cache are provided
so the processor can maintain cache consistency.
• On-Chip Memory Management Unit — Address management and memory space protection
mechanisms maintain the integrity of memory in a multi-tasking and virtual memory
environment. The memory management unit supports both segmentation and paging.
• Burst Cycles — Burst transfers allow a new doubleword to be read from memory on each
bus clock cycle. This capability is especially useful for instruction prefetch and for filling
the internal cache.
• Write Buffers — The processor contains four write buffers to enhance the performance of
consecutive writes to memory. The processor can continue internal operations after a write
to these buffers, without waiting for the write to be completed on the external bus.
• Bus Backoff — If another bus master needs control of the bus during a processor-initiated
bus cycle, the Intel486 processor floats its bus signals, then restarts the cycle when the bus
becomes available again.
• Instruction Restart — Programs can continue execution following an exception that is
generated by an unsuccessful attempt to access memory. This feature is important for
supporting demand-paged virtual memory applications.
2-2
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processor.