Intel Embedded Intel486 Hardware Reference Manual page 329

1-3
#, defined,
4-29
16-bit bus cycles,
7-10
16-bit I/O interface,
4-3
16-bit memories,
7-22
2-2 cycles,
7-14
32-bit I/O interface,
4-3
32-bit memories,
386
see Intel386 processor
485Turbocache module,
486
see Intel486 processor
82357 integrated system peripheral (ISP),
82420EX PCIset
8-20
block diagram,
8-33
DMA controller,
8-24
host interface,
8-22
IB component,
8-30
ISA interface,
82557 LAN controller
7-52
block diagram,
7-52
bus operation,
7-53
control,
7-51
features,
7-52
initializing,
7-50
overview,
7-52
PCI bus interface,
7-38
82596CA coprocessor,
interfacing to Intel486 processor,
7-46
memory structure,
7-49
performance issues,
7-42
signals,
82C59A programmable interrupt
7-35 7-36
controller, to
4-29
8-bit bus cycles,
7-7
8-bit I/O interface, to
4-3
8-bit memories,
A
10-21
A.C. termination,
10-22
Active termination,
Address bus
interface to I/O devices,
7-23
Address decoding,
7-5
for I/O devices,
4-1
Address signals,
7-12
to
7-16
to
9-12
8-7
7-41
to
7-44 7-45
to
7-9
7-6
3-14
ALU,
Applications of the Intel486 processor,
1-4
Assert, defined,
B
Block diagrams
8-20
82420EX PCIset,
82557 LAN Controller,
lntel486 SX processor,
lntelDX2 and IntelDX4 processors,
peripheral subsystem example,
ULP lntel486 SX and ULP Intel486 GX
3-4
processors,
6-10
Block size, in cache,
10-39
Breakpoint instruction,
Broadcasting cache data,
4-50 4-52
Burst cycles, to
access lengths of CPU functions,
5-1
memory logic and,
5-3
typical cycle,
5-2
writes,
4-26 4-29
Burst mode, to
9-9
wait states in,
Bus arbitration
in a multi-processor system,
in a single-processor system,
7-26
Bus contention,
7-20
Bus control logic, to
7-21
Bus control signals,
Bus cycles
5-2
access length,
9-6
mix of, with cache,
4-38
Bus hold,
3-7
Bus interface unit, to
4-14
Bus masters, multiple,
Bus throttle timers, 82596CA coprocessor,
Bus, see Processor bus or System bus
4-1
Byte enables,
4-8
Byte swapping,
INDEX
2-11
7-52
3-3
3-2
7-17
6-14
5-2
4-14 4-15
to
4-12 4-13
to
7-23
7-22
to
3-8
7-49
Index-1