4.3.12 Bus Cycle Restart - Intel Embedded Intel486 Hardware Reference Manual

4.3.12 Bus Cycle Restart

In a multi-master system, another bus master may require the use of the bus to enable the Intel486
processor to complete its current bus request. In this situation, the Intel486 processor must restart
its bus cycle after the other bus master has completed its bus transaction.
A bus cycle may be restarted if the external system asserts the backoff (BOFF#) input. The
Intel486 processor samples the BOFF# pin every clock cycle. When BOFF# is asserted, the
Intel486 processor floats its address, data, and status pins in the next clock (see
4-34). Any bus cycle in progress when BOFF# is asserted is aborted and any data returned to the
processor is ignored. The pins that are floated in response to BOFF# are the same as those that
are floated in response to HOLD. HLDA is not generated in response to BOFF#. BOFF# has
higher priority than RDY# or BRDY#. If either RDY# or BRDY# are asserted in the same clock
as BOFF#, BOFF# takes effect.
Ti
CLK
ADS#
A31–A2
M/IO#
D/C#
BE3#–BE0#
RDY#
BRDY#
KEN#
BOFF#
BLAST#
DATA
†
To Processor
T1 T2 Tb Tb
100
Figure 4-33. Restarted Read Cycle
T1b T2 T2 T2
100 104
†
†
BUS OPERATION
Figures 4-33 and
T2 T2
108 10C
†
†
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