Bus Interface Unit; Bus Interface Unit - Intel Embedded Intel486 Hardware Reference Manual

CLK
Instruction
Fetch
The internal pipelining on the Intel486 processor offers an important performance advantage over
many single-clock RISC processors: in the Intel486 processor, data can be loaded from the cache
with one instruction and used by the next instruction in the next clock. This performance advan-
tage results from the stage-1 decode step, which initiates memory accesses before the execution
cycle. Because most compilers and application programs follow load instructions with instruc-
tions that operate on the loaded data, this method optimizes the execution of existing binary code.
The method has a performance trade-off: an instruction sequence that changes register contents
and then uses that register in the next instruction to access memory takes three clocks rather than
two. This trade-off is only a minor disadvantage, however, since most instructions that access
memory use the stable contents of the stack pointer or frame pointer, and the additional clock is
not used very often. Compilers often place an unrelated instruction between one that changes an
addressing register and one that uses the register. Such code is compatible with the Intel386 pro-
cessor, and the Intel486 processor provides special stack increment/decrement hardware and an
extra register port to execute back-to-back stack push/pop instructions in a single clock.
3.2

BUS INTERFACE UNIT

The bus interface unit prioritizes and coordinates data transfers, instruction prefetches, and con-
trol functions between the processor's internal units and the outside system. Internally, the bus
interface unit communicates with the cache and the instruction prefetch units through three 32-
bit buses, as shown in
signals, described in Chapter 3. Except for cycle definition signals, all external bus cycles, mem-
ory reads, instruction prefetches, cache line fills, etc., look like conventional microprocessor cy-
cles to external hardware, with all cycles having the same bus timing.
Stage-1
Decode
Figure 3-4. Internal Pipelining
Figure 3-1. Externally, the bus interface unit provides the processor bus
INTERNAL ARCHITECTURE
Stage-2
Decode
Execution
Register
Write-back
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