Address Decoder - Intel Embedded Intel486 Hardware Reference Manual

Figure 7-10 shows PLD equations for basic I/O control logic. A wait state generator should be
implemented to optimize wait state generation.
Inputs ADS#, M/IO#, D/C#, W/R#, SEL0, SEL1, SEL2
Outputs IOCYC, 0 C1, C2, IOR#, IOW#, RDY#
IOCYC = IOCYCLE VALID
C0, C1, C2 = Outputs of a 3-bit counter
Sel 0, 1, 2 = Programmable wait state select input
PLD Equation:
IO VALID CYCLE;
IOCYC : =ADS * M/IO# *D/C
Wait State Counter;
C0 : = IOCYC * C0#
C1 : = IOCYC * C0 * C1#
C2 : = IOCYC * C0 * C1 * C2#
I/O Read; I/O Write
IOR : = ADS * M/IO# * D/C * W/R#
+ IOR * RDY
IOW : = ADS * M/IO * D/C * W/R
+ IOW * RDY#
READY (3 Wait States)
RDY = C0 * C1 * C2#
Figure 7-10. PLD Equations for Basic I/O Control Logic
The equation in Figure 7-10
wait state logic inserts the needed wait states according to the number required by the device be-
ing accessed. In a simple design, I/O accesses can be designated as being equal to the number of
wait states required by the slowest device.
7.2.4

Address Decoder

The function of the address decoder is to decode the most significant address bits and generate
address select signals for each system device. The address space is divided into blocks, and the
address select signals indicate whether the address on the address bus is within the predetermined
range. The block size usually represents the amount of address space that can be accessed within
a particular device and the address select signal is asserted for any address within that range.
+ IOCYC * C0# * C1
+ IOCYC * C0# * C2
+ IOCYC * C0# * C1 * C2
shows an implementation of a seven-state wait state controller. The
PERIPHERAL SUBSYSTEM
; start I/O cycle
;END when ready
;Counter bit 0
;Counter bit 1
;Counter bit 2
7-23