Inteldx2™ And Inteldx4™ Processors Floating-Point Error Handling In At-Compatible Systems - Intel Embedded Intel486 Hardware Reference Manual

3. Exceptions other than on all transcendental instructions, integer arithmetic instructions,
FSQRT, FSCALE, FPREM(1), FXTRACT, FBLD, and FBSTP.
4. Any exception on all basic arithmetic, load, compare, and control instructions (i.e., all
other instructions).
For both sets of exceptions above, the Intel387 math coprocessor asserts ERROR# when the error
occurs and does not wait for the next floating-point instruction to be encountered.
IGNNE# is an input to the IntelDX2 and IntelDX4 processors. When the NE bit in CR0 is cleared,
and IGNNE# is asserted, the IntelDX2 and IntelDX4 processors ignore user floating-point errors
and continue executing floating-point instructions. When IGNNE# is deasserted, the IGNNE# is
an input to these processors that freeze on floating-point instructions that get errors (except for
the control instructions FNCLEX, FNINIT, FNSAVE, FNSTENV, FNSTCW, FNSTSW,
FNSTSW AX, FNENI, FNDISI and FNSETPM). IGNNE# may be asynchronous to the IntelDX2
and IntelDX4 processor clock.
In systems with user-defined error reporting, the FERR# pin is connected to the interrupt control-
ler. When an unmasked floating-point error occurs, an interrupt is raised. If IGNNE# is high at
the time of this interrupt, the IntelDX2 and IntelDX4 processors freeze (disallowing execution of
a subsequent floating-point instruction) until the interrupt handler is invoked. By driving the
IGNNE# pin low (when clearing the interrupt request), the interrupt handler can allow execution
of a floating-point instruction, within the interrupt handler, before the error condition is cleared
(by FNCLEX, FNINIT, FNSAVE or FNSTENV). If execution of a non-control floating-point in-
struction, within the floating-point interrupt handler, is not needed, the IGNNE# pin can be tied
high.
4.3.15 IntelDX2™ and IntelDX4™ Processors Floating-Point Error Handling in
AT-Compatible Systems
The IntelDX2 and IntelDX4 processors provide special features to allow the implementation of
an AT-compatible numerics error reporting scheme. These features DO NOT replace the external
circuit. Logic is still required that decodes the OUT F0 instruction and latches the FERR# signal.
The use of these Intel Processor features is described below.
•
The NE bit in the Machine Status Register
•
The IGNNE# pin
•
The FERR# pin
The NE bit determines the action taken by the IntelDX2 and IntelDX4 processors when a numer-
ics error is detected. When set, this bit signals that non-DOS compatible error handling is imple-
mented. In this mode the IntelDX2 and IntelDX4 processors take a software exception (16) if a
numerics error is detected.
If the NE bit is reset, the IntelDX2 and IntelDX4 processors use the IGNNE# pin to allow an ex-
ternal circuit to control the time at which non-control numerics instructions are allowed to exe-
cute. Note that floating-point control instructions such as FNINIT and FNSAVE can be executed
during a floating-point error condition regardless of the state of IGNNE#.
BUS OPERATION
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