Second-Level Cache Performance Considerations - Intel Embedded Intel486 Hardware Reference Manual

100%
90%
80%
75%
60%
50%
40%
30%
20%
10%
2-1-2
Figure 9-4. Effect of External Bus Utilization versus Wait States
The bus utilization percentage is not critical for single-processor systems. However, when con-
sidering multi-processing systems, the amount of time that each CPU needs the bus becomes very
important.
9.6

SECOND-LEVEL CACHE PERFORMANCE CONSIDERATIONS

9.6.1 Advantages of a Second-Level Cache
As previously described, approximately 90%-95% of the read cycles generated internally by the
Intel486 processor will be satisfied by the processor's on-chip cache. However, the remaining
5%-10% that miss the internal cache will result in external read bus cycles being executed. For
best system performance, an external (L2) cache reduces wait states for these read cycles.
This section discusses the use of a L2 cache. Different applications and operating environments
experience varying performance benefits from use of an L2 cache. Hit rates for L2 caches depend
on the application being executed and the randomness with which the application addresses mem-
ory. Systems which make extensive use of multi-tasking should see a very beneficial gain in sys-
tem performance with use of a L2 cache.
Intel486™ Processor External Bus Utilization
vs. Memory Latency
3-1-2 4-1-2 2-1-3
Memory Latency
PERFORMANCE CONSIDERATIONS
3-1-3 2-2-2 4-1-4 5-1-4
9-11