Burst And Cache Line Fill Order - Intel Embedded Intel486 Hardware Reference Manual

4.3.4.2

Burst and Cache Line Fill Order

The burst order used by the Intel486 processor is shown in
by any burst cycle (cache or not), cache line fill (burst or not) or code prefetch.
The Intel486 processor presents each request for data in an order determined by the first address
in the transfer. For example, if the first address was 104 the next three addresses in the burst will
be 100, 10C and 108. An example of burst address sequencing is shown in
Table 4-8. Burst Order (Both Read and Write Bursts)
First Address
0
4
8
C
Ti
CLK
ADS#
A31–A2
RDY#
BRDY#
KEN#
BLAST#
DATA
†
To Processor
Figure 4-18. Burst Cycle Showing Order of Addresses
The sequences shown in
with 32-bit data buses. The sequence applies to all bursts, regardless of whether the purpose of
the burst is to fill a cache line, perform a 64-bit read, or perform a pre-fetch. If either BS8# or
BS16# is asserted, the Intel486 processor completes the transfer of the current 32-bit word before
Second Address
4
0
C
8
T1 T2
104
Table 4-8 accommodate systems with 64-bit buses as well as systems
Table 4-8. This burst order is followed
Third Address Fourth Address
8
C
0
4
T2 T2
100 10C
†
†
BUS OPERATION
Figure 4-18.
C
8
4
0
T2 Ti
108
†
†
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