Intel Embedded Intel486 Hardware Reference Manual page 46

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
64-Bit Interunit Transfer Bus
Base/
Barrel Segmentation
Index
Shifter
Bus
Register 32
File
ALU
Attribute PLA
Micro-
Instruction
Control &
Floating
Protection
Point Unit
Test Unit
Floating
Control
Point
ROM
Register File
Figure 3-1. IntelDX2™ and IntelDX4™ Processors Block Diagram
3-2
32-Bit Data Bus
32-Bit Data Bus
Linear Address 32
PCD
PWT
Paging
Unit
Unit
20
Descriptor
Physical
Registers
Address
Translation
Limit and
Lookaside
Buffer
Displacement Bus
32
Code
Stream
Instruction
24
Decode
Decoded
Instruction
Path
Core
Clock
2
Cache Unit
32
8 Kbyte Cache
(DX2)
32
16 Kbyte Cache
(DX4)
32
Prefetcher
32-Byte Code
Queue
2x16 Bytes
CLK
Clock
Multiplier
Bus Interface
A31-A2
BE3#- BE0#
Address
Drivers
Write Buffers
4 x 32
D31-D0
Data Bus
Transceivers
ADS# W/R# D/C# M/IO#
Bus Control
PCD PWT RDY# LOCK#
PLOCK# BOFF# A20M#
BREQ HOLD HLDA
RESET SRESET INTR
NMI SMI# SMIACT#
FERR# IGNNE#
STPCLK#
Request
Sequencer
BRDY# BLAST#
Burst Bus
Control
BS16# BS8#
Bus Size
Control
KEN# FLUSH#
Cache
AHOLD EADS#
Control
Parity DP3-DP0 PCHK#
Generation
and Control
TCK TMS
Boundary
TDI TD0
Scan
Control
A5439-01