Intel Embedded Intel486 Hardware Reference Manual page 273

PERFORMANCE CONSIDERATIONS
9.5.2 Wait States in Burst and Non-Burst Modes
The Intel486 processor can execute non-burst cycles in as little as two clocks. These cycles are
called 2-2 cycles, as read and write cycles take two cycles each. The first 2 refers to read cycle
time and the second 2 to write cycle time. Accesses to devices that cannot respond by the end of
the second clock require the addition of wait states. If a wait state must be added to write cycles,
then a 2-3 system is created. The external system generates RDY# and the RDY# signal is sam-
pled at the end of the second clock. If it is asserted (low) at the sample time, it indicates that the
external system has placed valid data on the pins for reads, or that the system has accepted the
data for writes. Wait states are inserted by driving RDY# inactive (high) at the end of the second
clock.
The Intel486 processor non-burst cycles are very similar to non-pipelined Intel386™ DX CPU
cycles. In the Intel386 DX processor, the read and write accesses can be as fast as two cycles each.
Thus, adding a wait state increases the bus cycle time by 50 percent of the zero wait state bus
cycle time. Overall performance does not degrade in direct proportion to the bus cycle increase.
To enhance read performance, the Intel486 processor supports burst cycles. The Intel486 proces-
sor bus can burst successive words from memory into the cache every clock. Most memory reads
can be performed in bursts as indicated by the BLAST# pin. The Intel486 processor keeps the
BLAST# output inactive in the second clock of the cycle, indicating that it is able to perform a
burst cycle. The external system indicates that it will initiate a burst cycle by asserting BRDY#.
If BRDY# is not asserted at the second clock, wait states are inserted. If a system executes non-
burst reads in two clocks, burst reads in one clock, and writes in three clocks, a 2-1-3 system is
indicated.
Because of the on-chip cache, the addition of external wait states affects the Intel486 processor's
performance less than previous processors. A wait state in a Intel386 DX system incurs a perfor-
mance degradation of about 20 percent. The Intel486 processor achieves optimum performance
through a 2-1-2, zero wait state bus cycle. Adding one wait state in an Intel486 processor system
causes a performance degradation of only about 6 percent.
The Intel486 processor can execute an external bus cycle in as little as two clock cycles. For
achieving the optimum system performance, memory accesses must also execute in two cycles
to eliminate wait states. At higher frequencies, however, it is impractical and cost-prohibitive to
implement zero wait states for all memory.
At 25 MHz, a wait state adds 40 ns to the available access time. While an operation with one wait
state increases the bus cycle time by 50 percent, system performance does not degrade in direct
proportion. The amount of degradation incurred is application-dependent and varies with instruc-
tion mix, external cache size, and the number of memory references.
Several DRAM design techniques can reduce wait states and keep system performance at a high
level using slower memory devices. These techniques, page mode design and interleaving, and
their impact on performance, are discussed in Chapter 5.
9-9