Bus Hold - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
4.3.9

Bus Hold

The Intel486 processor provides a bus hold, hold acknowledge protocol using the bus hold re-
quest (HOLD) and bus hold acknowledge (HLDA) pins. Asserting the HOLD input indicates that
another bus master has requested control of the Intel486 processor bus. The Intel486 processor
responds by floating its bus and asserting HLDA when the current bus cycle, or sequence of
locked cycles, is complete. An example of a HOLD/HLDA transaction is shown in
Unlike the Intel386 processor, the Intel486 processor can respond to HOLD by floating its bus
and asserting HLDA while RESET is asserted.
Ti
CLK
ADS#
A31–A2
M/IO#
D/C#
W/R#
BE3#–BE0#
RDY#
DATA
HOLD
HLDA
‡
From Processor
Note that HOLD is recognized during un-aligned writes (less than or equal to 32 bits) with
BLAST# being asserted for each write. For a write greater than 32-bits or an un-aligned write,
HOLD# recognition is prevented by PLOCK# getting asserted. However, HOLD is recognized
during non-cacheable, non-burstable code prefetches even though PLOCK# is asserted.
4-38
Ti T1
Figure 4-29. HOLD/HLDA Cycles
T2 Ti
‡
Figure 4-29.
Ti T1
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