Table of Contents
Advertisement
the cache unit. The contents of the general purpose registers are sent to the segmentation unit on
a separate 32-bit bus for generation of effective addresses.
3.8
FLOATING-POINT UNIT
The floating-point unit executes the same instruction set as the 387 math coprocessor. The unit
contains a push-down register stack and dedicated hardware for interpreting the 32-, 64-, and 80-
bit formats as specified in IEEE Standard 754. An output signal passed through to the processor
bus indicates floating-point errors to the external system, which in turn can assert an input to the
processor indicating that the processor should ignore these errors and continue normal operations.
3.8.1
IntelDX2™ and IntelDX4™ Processor On-Chip Floating-Point Unit
The IntelDX2 and IntelDX4 processors incorporate the basic Intel486 processor 32-bit architec-
ture, with on-chip memory management and cache memory units. They also have an on-chip
floating-point unit (FPU) that operates in parallel with the arithmetic and logic unit. The FPU pro-
vides arithmetic instructions for a variety of numeric data types and executes numerous built-in
transcendental functions (e.g., tangent, sine, cosine, and log functions). The floating-point unit
fully conforms to the ANSI/IEEE standard 754-1985 for floating-point arithmetic.
All software written for the Intel386 processor, Intel387 math coprocessor and previous members
of the 86/87 architectural family runs on these processors without modifications.
3.9
SEGMENTATION UNIT
A segment is a protected, independent address space. Segmentation is used to enforce isolation
among application programs, to invoke recovery procedures, and to isolate the effects of pro-
gramming errors.
The segmentation unit translates a segmented address issued by a program, called a logical ad-
dress, into an unsegmented address, called a linear address. The locations of segments in the lin-
ear address space are stored in data structures called segment descriptors. The segmentation unit
performs its address calculations using segment descriptors and displacements (offsets) extracted
from instructions. Linear addresses are sent to the paging and cache units. When a segment is ac-
cessed for the first time, its segment descriptor is copied into a processor register. A program can
have as many as 16,383 segments. Up to six segment descriptors can be held in processor regis-
ters at a time.
Figure 3-6
shows the relationships between logical, linear, and physical addresses.
INTERNAL ARCHITECTURE
3-15
Advertisement
Chapters
Table of Contents
