Intel Embedded Intel486 Hardware Reference Manual page 103

For cacheable and non-burst or burst cycles, HOLD is acknowledged during backoff only if
HOLD and BOFF# are asserted during an active bus cycle (after ADS# asserted) and before the
first RDY# or BRDY# has been asserted (see
BOFF# are asserted is unimportant (as long as both are asserted prior to the first RDY#/BRDY#
asserted by the system).
be asserted simultaneously or after BOFF# and still be acknowledged.
The pins floated during bus hold are: BE3#–BE0#, PCD, PWT, W/R#, D/C#, M/O#, LOCK#,
PLOCK#, ADS#, BLAST#, D31–D0, A31–A2, and DP3–DP0.
Ti
CLK
ADS#
M/IO#
D/C#
W/R#
KEN#
BRDY#
RDY#
HOLD
HLDA
BOFF#
Figure 4-30. HOLD Request Acknowledged during BOFF#
Figure 4-30 shows the case where HOLD is asserted first; HOLD could
Ti Ti Ti Ti
Figure 4-30). The order in which HOLD and
T1 T2 Ti
BUS OPERATION
Ti Ti Ti
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