Intel Embedded Intel486 Hardware Reference Manual page 233

SYSTEM BUS DESIGN
The EBC interfaces the host bus to the EISA/ISA bus. It provides compatibility with EISA/ISA
bus cycles for EISA/ISA standard memory or I/O cycles, zero-wait state cycles, compressed cy-
cles and burst cycles. It also translates host bus cycles to EISA/ISA bus cycles and vice versa. It
generates ISA signals for EISA masters and EISA signals for ISA masters and it supports host
and EISA/ISA refresh cycles. The EBC supports 8-, 16-, and 32-bit DMA transfers and interacts
with the DMA controller. It provides byte-assembly and disassembly for 8-, 16-, and 32-bit data
transfers. The EBC generates the appropriate data conversion and assembly control signals to fa-
cilitate transfers of various data widths between the host and ISA and EISA buses. The EBC posts
processor-to-EISA/ISA write cycles to improve system performance and provides I/O recovery
time between back-to-back I/O cycles. Figure 8-2 shows a detailed block diagram of the EBC and
its various interface signals to the host, the EISA, ISA, ISP units and the data and address con-
trols. The interfaces are discussed later in this chapter.
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