Intel Embedded Intel486 Hardware Reference Manual page 326

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
10.8.5 Debug Control Register (DR7)
A debug control register, DR7 shown in
as enabling the breakpoints and setting up several control options for the breakpoints. There are
several fields within the debug control register. These are discussed below:
LENi (breakpoint length specification bits). A 2-bit LEN field exists for each of the four break-
points. It specifies the length of the associated breakpoint field. It is possible to have three differ-
ent choices: 1 byte, 2 bytes and 4 bytes. LENi field encoding is shown in
RW Encoding
The LENi field controls the size of the breakpoint field i by controlling whether all the low order
linear address bits in the breakpoint address register are used to detect the breakpoint event.
Therefore, all breakpoint fields are aligned: 2-byte breakpoint fields begin on word boundaries,
and 4-byte breakpoint fields begin on dword boundaries.
A 2-bit RW field exists for each of the four breakpoints. The 2-bit field specifies the type of usage
which must occur in order to activate the associated breakpoint.
RW encoding 00 is used to setup an instruction execution breakpoint. RW encodings 01 or 11 are
used to setup write only or read-only or read/write data breakpoints. The data breakpoint can be
setup by writing the linear address into DRi. For data breakpoints, RWi can:
= 01 M write only
= 11 M read/write
LENi = 00, 01, 11.
An instruction execution breakpoint can be setup by writing the address of the beginning of the
instruction into DRi. RWi must equal 00 and LENi must equal 00 for instruction execution break-
points. If the instruction beginning at the breakpoint address is about to be executed, the
instruction execution breakpoint has occurred, and the breakpoint is enabled, an exception 1 fault
occurs before the instruction is executed.
GD (Global Debug Register access detect). The debug registers can only be accessed in real
mode or at privilege level 0 in Protected Mode. The GD bit when set provides extra protection
against any debug register access even in Real Mode or at privilege level 0 in Protected Mode.
This additional protection feature is provided to guarantee that a software debugger can have full
control over the debug register resources when required.
The breakpoint mechanism of the Intel486 processors differs from that of the Intel386™ micro-
processor. The Intel486 processor always does exact data breakpoint matching regardless of the
GE/LE bit settings. Any data breakpoint trap is reported after completion of the instruction that
10-42
Figure 10-31
Table 10-2. LENi Fields
Usage Causing Breakpoint
00 Instruction execution only
01
10 Undefined—Do not use this encoding
11 Data reads and writes only
allows several debug control functions such
Data writes only
Table 10-2.