Instruction Prefetch Unit; Instruction Prefetch Unit - Intel Embedded Intel486 Hardware Reference Manual

Write-through
Cache Enabled
Enabled
no
no
yes
yes
When caching is enabled, memory reads and instruction prefetches are cacheable. These transfers
are cached if external logic asserts the cache enable input in that bus cycle, and if the current page
table entry allows caching. During cycles in which caching is disabled, cache lines are not filled
on cache misses. However, the cache remains active even though it is disabled for further filling.
Data already in the cache is used if it is still valid. When all data in the cache is flagged invalid,
as happens in a cache flush, all internal read requests are propagated as bus cycles to the external
system.
When cache write-through is enabled, all writes, including those that are cache hits, are written
through to memory. Invalidation operations remove a line from cache if the invalidate address
maps to a cache line. When cache write-throughs are disabled, an internal write request that is a
cache hit does not cause a write-through to memory, and cache invalidation operations are dis-
abled. With both caching and cache write-through disabled, the cache can be used as a high-speed
static RAM. In this configuration, the only write cycles that are propagated to the processor bus
are cache misses, and cache invalidation operations are ignored.
The IntelDX4 processor can also be configured to use a write-back cache policy. For detailed in-
formation on the Intel486 processor cache feature, and on the Write-Back Enhanced IntelDX4
processor, refer to Chapter 6, "Cache Subsystem."
3.4

INSTRUCTION PREFETCH UNIT

When the bus interface unit is not performing bus cycles to execute an instruction, the instruction
prefetch unit uses the bus interface unit to prefetch instructions. By reading instructions before
they are needed, the processor rarely needs to wait for an instruction prefetch cycle on the pro-
cessor bus.
Instruction prefetch cycles read 16-byte blocks of instructions, starting at addresses numerically
greater than the last-fetched instruction. The prefetch unit, which has a direct connection (not
shown in Figure 3-1) to the paging unit, generates the starting address. The 16-byte prefetched
blocks are read into both the prefetch and cache units simultaneously. The prefetch queue in the
prefetch unit stores 32 bytes of instructions. As each instruction is fetched from the queue, the
code part is sent to the instruction decode unit and (depending on the instruction) the displace-
ment part is sent to the segmentation unit, where it is used for address calculation. If loops are
Table 3-2. Cache Configuration Options
no Cache line fills, cache write-throughs, and cache invalidations are
disabled. This configuration allows the internal cache to be used as
high-speed static RAM.
yes Cache line fills are disabled, and cache write-throughs and cache
invalidations are enabled. This configuration allows software to
disable the cache for a short time, then re-enable it without flushing
the original contents.
no INVALID
yes Cache line fills, cache write-throughs, and cache invalidations are
enabled. This is the normal operating configuration.
INTERNAL ARCHITECTURE
Operating Mode
3-13