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3.3 Logic Analyzer Connectors J1 and J5
Table 3-3 Logic Analyzer Connector J1 Signal Descriptions
Pin
1, 2, 6
3
4
5
7, 9
8
10
11
12 — 19
AD7 — AD0
20
M68EML08EY Emulation Module - Version 1.0
24
Connectors J1 and J5 are the EML08EY logic analyzer connectors. Figure 3-3
and Table 3-3 give pin assignments and signal descriptions for connector J1,
which has pod 1 signals. Figure 3-4 and Table 3-4 give pin assignments and
signal descriptions for connector J5, which has pod 2 signals.
Figure 3-3 Logic Analyzer Connector J1 Pin Assignments
Label
NC
No connection
T12
SYSTEM BUS CLOCK — Clock that matches the internal emulation
MCU bus clock
LBOX
LAST BUS CYCLE — Output signal that the emulator asserts to
indicate that the target system MCU is in the last bus cycle of an
instruction .
RST_B
COP RESET — Active-low output signal indicating (1) the target driving
its reset pin, or (2) the platform board driving a reset to the emulator
module.
TEST
Test pins are used only during system development and factory test.
EMUX
MUXED CONTROL — Output from the emulation MCU that, during
different phases of the clock, drives R/W, LIR_B, and LAST signals.
LRW
LATCHED READ/WRITE — Output signal from the target MCU. If high,
the target MCU is reading. If low, the target MCU is writing.
LIR_B
LOAD INSTRUCTION REGISTER — Active-low output signal
indicating that the target MCU is fetching an instruction.
PFB DATA BUS (lines 7—0) — Outputs the data lines going to the
platform board.
GND
GROUND
Support Information
J1
• •
NC 1
2
• •
T12 3
4
• •
RST_B 5
6
• •
TEST 7
8
• •
TEST 9
10
• •
LIR_B 11
12
• •
AD6 13
14
• •
AD4 15
16
• •
AD2 17
18
• •
AD0 19
20
Signal
NC
LBOX
NC
EMUX
LRW
AD7
AD5
AD3
AD1
GND
User's Manual
MOTOROLA
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