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Instruction Timing
certain hardware resources within the processor are marked as busy for two clock
cycles after the final DSOC cycle of the store instruction. If a subsequent store
instruction is encountered within this two-cycle window, it is stalled until the
resource again becomes available. Thus, the maximum pipeline stall involving
consecutive store operations is two cycles.
• The OEP can complete all memory accesses without memory causing any stall
conditions. Thus, timing details in this section assume an infinite zero-wait state
memory attached to the core.
• All operand data accesses are assumed to be aligned on the same byte boundary as
the operand size:
— 16-bit operands aligned on 0-modulo-2 addresses
— 32-bit operands aligned on 0-modulo-4 addresses
Operands that do not meet these guidelines are misaligned. Table 2-9 shows how the
core decomposes a misaligned operand reference into a series of aligned accesses.
A[1:0]
x1
x1
10
1
Each timing entry is presented as C(r/w), described as follows:
C is the number of processor clock cycles, including all applicable operand fetches and writes, as
well as all internal core cycles required to complete the instruction execution.
r/w is the number of operand reads (r) and writes (w) required by the instruction. An operation
performing a read-modify write function is denoted as (1/1).
2.7.1 MOVE Instruction Execution Times
The execution times for the MOVE.{B,W,L} instructions are shown in the next tables.
Table 2-12 shows the timing for the other generic move operations.
For all tables in this section, the execution time of any
instruction using the PC-relative effective addressing modes is
equivalent to the time using comparable An-relative mode.
ET with {<ea> = (d16,PC)}
ET with {<ea> = (d8,PC,Xi*SF)}
The nomenclature "(xxx).wl" refers to both forms of absolute
addressing, (xxx).w and (xxx).l.
2-30
Table 2-9. Misaligned Operand References
Size
Word
Byte, Byte
Long
Byte, Word, Byte
Long
Word, Word
NOTE:
equals ET with {<ea> = (d16,An)}
equals ET with {<ea> = (d8,An,Xi*SF)}
MCF5272 User's Manual
Bus Operations
2(1/0) if read
1(0/1) if write
3(2/0) if read
2(0/2) if write
2(1/0) if read
1(0/1) if write
1
Additional C(R/W)
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