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The user can control the extent to which level 4 interrupts may interrupt other
level 4 interrupts by selectively clearing the ISR. A new INRQ interrupt will
be processed if it has a higher priority than the highest priority INRQ interrupt
having its ISR bit set. Thus, if an INRQ interrupt routine lowers the 3-bit mask
in the M68000 core to level 3 and also clears its ISR bit at the beginning of
the interrupt routine, then a lower priority INRQ interrupt can interrupt it as
long as the lower priority is higher than any other ISR bits that are set.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
I
PB11
I
PB10
I
scc1
I
SDMA
j
mMA
I
scc2
I
TIMER1
I
scc3
I
PBS
I
TIMER2
j
scP
I
TIMER3
I
sMc1
I
sMc2
I
PBS
I - I
3.3 PARALLEL 1/0 PORTS
The IMP supports two general-purpose 1/0 ports, port A and port B, whose
pins can be general-purpose 1/0 pins or dedicated peripheral interface pins.
Some port B pins are always maintained as four general-purpose 1/0 pins,
each with interrupt capability.
3.3.1 Port A
3-28
Each of the 16 port A pins are independently configured as a general-purpose
1/0 pin if the corresponding port A control register (PACNT) bit is cleared.
Port A pins are configured as dedicated on-chip peripheral pins if the cor-
responding PACNT bit is set.
When acting as a general-purpose 1/0 pin, the signal direction for that pin is
determined by the corresponding control bit in the port A data direction
register (PADDR). The port 1/0 pin is configured as an input if the corre-
sponding PADDR bit is cleared; it is configured as an output if the corre-
sponding PADDR bit is set. All PACNT bits and PADDR bits are cleared on
total system reset, configuring all port A pins as general-purpose input pins.
If a port A pin is selected as a general-purpose 1/0 pin, it may be accessed
through the port A data register (PADAT). Data written to the PADAT is stored
in an output latch. If a port A pin is configured as an output, the output latch
data is gated onto the port pin. In this case, when the PADAT is read, the
contents of the output latch associated with the output port pin are read. If
a port A pin is configured as an input, data written to PADAT is still stored
in the output latch but is prevented from reaching the port pin. In this case,
when PADAT is read, the state of the port pin is read.
MC68302 USER'S MANUAL
MOTOROLA
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