Agilent Technologies N1996A-503 User Reference page 328

Using The Status Monitoring Subsystem
Using a Status Register
Using a Status Register
Each bit in a register is represented by a numerical value based on its location. See figure
below. This number is sent with the command to enable a particular bit. If you want to
enable more than one bit, you would send the sum of all the bits that you want to monitor.
Figure 6-1 Figure: Status Register Bit Values
NOTE: Bit 15 is not used to report status.
Example 1:
1. To enable bit 0 and bit 6 of standard event status register, you would send the command
*ESE 65 because 1 + 64 = 65.
2. The results of a query are evaluated in a similar way. If the *STB? command returns a
decimal value of 140, (140 = 128 + 8 + 4) then bit 7 is true, bit 3 is true and bit 2 is true.
Example 2:
1. Suppose you want to know if an ADC over range occurs, and you only cared about that
specific condition. So you would want to know what was happening with bit 4 in the
Status Questionable Integrity register, and not about any other bits.
2. It's usually a good idea to start by clearing all the status registers with *CLS.
3. Sending the STAT:QUES:INT:ENAB 16 command lets you monitor only bit 4 events,
instead of the default monitoring all the bits in the register. The register default is for
positive transition events (0 to 1 transition). That is, when an ADC over range occurs. If
instead, you wanted to know when the ADC over range condition is cleared, then you
would set the STAT:QUES:INT:PTR 0 and the STAT:QUES:INT:NTR 32767.
4. So now the only output from the Status Questionable Integrity register will come from a
bit 4 positive transition. That output goes to the Integrity Sum bit 9 of the Status
Questionable register.
328 Chapter 6