Low Power Modes - ST STM32L4 5 Series Reference Manual

Power control (PWR)
Low-power run mode
Mode exit
Wakeup latency
5.3.3

Low power modes

Entering low power mode
Low power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or
WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex
System Control register is set on Return from ISR.
Entering Low-power mode through WFI or WFE will be executed only if no interrupt is
pending or no event is pending.
Exiting low power mode
From Sleep modes, and Stop modes the MCU exit low power mode depending on the way
the low power mode was entered:
•
If the WFI instruction or Return from ISR was used to enter the low power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the device.
•
If the WFE instruction is used to enter the low power mode, the MCU exits the low
power mode as soon as an event occurs. The wakeup event can be generated either
by:
–
–
From Standby modes, and Shutdown modes the MCU exit low power mode through an
external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins
168/1830
LPR = 0
Wait until REGLPF = 0
Increase the system clock frequency
Regulator wakeup time from low-power mode
NVIC IRQ interrupt.
- When SEVONPEND = 0 in the Cortex
an interrupt in the peripheral control register and in the NVIC. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared.
Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
- When SEVONPEND = 1 in the Cortex
By enabling an interrupt in the peripheral control register and optionally in the
NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and
when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt
clear pending register) have to be cleared.
All NVIC interrupts will wakeup the MCU, even the disabled ones. Only enabled
NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
Event
Configuring a EXTI line in event mode. When the CPU resumes from WFE, it is
not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ
channel pending bit as the pending bits corresponding to the event line is not set.
It may be necessary to clear the interrupt flag in the peripheral.
DocID024597 Rev 5
Table 24. Low-power run
Description
®
-M4 System Control register. By enabling
®
-M4 System Control register.
RM0351
®
-M4