ST STM32L4 5 Series Reference Manual page 260

Reset and clock control (RCC)
Bit 31 LPTIM1SMEN: Low power timer 1 clocks enable during Sleep and Stop modes
Bit 30 OPAMPSMEN: OPAMP interface clocks enable during Sleep and Stop modes
Bit 29 DAC1SMEN: DAC1 interface clocks enable during Sleep and Stop modes
Bit 28 PWRSMEN: Power interface clocks enable during Sleep and Stop modes
Bit 27 Reserved, must be kept at reset value.
Bit 26 CAN2SMEN: CAN2 clocks enable during Sleep and Stop modes (This bit is reserved for
STM32L475xx/476xx/486xx devices)
0: CAN2 clocks disabled by the clock gating(1) during Sleep and Stop modes
1: CAN2 clocks enabled by the clock gating(1) during Sleep and Stop modes
Bit 25 CAN1SMEN: CAN1 clocks enable during Sleep and Stop modes
Bit 24 CRSSMEN: CRS clock enable during Sleep and Stop modes (This bit is reserved for
STM32L475xx/476xx/486xx devices)
Bit 23 I2C3SMEN: I2C3 clocks enable during Sleep and Stop modes
Bit 22 I2C2SMEN: I2C2 clocks enable during Sleep and Stop modes
Bit 21 I2C1SMEN: I2C1 clocks enable during Sleep and Stop modes
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Set and cleared by software.
0: LPTIM1 clocks disabled by the clock gating
1: LPTIM1 clocks enabled by the clock gating
Set and cleared by software.
0: OPAMP interface clocks disabled by the clock gating
1: OPAMP interface clocks enabled by the clock gating
Set and cleared by software.
0: DAC1 interface clocks disabled by the clock gating
1: DAC1 interface clocks enabled by the clock gating
Set and cleared by software.
0: Power interface clocks disabled by the clock gating
1: Power interface clocks enabled by the clock gating
Set and cleared by software
Set and cleared by software.
0: CAN1 clocks disabled by the clock gating
1: CAN1 clocks enabled by the clock gating
Set and cleared by software.
0: CRS clocks disabled by the clock gating
1: CRS clocks enabled by the clock gating
Set and cleared by software.
0: I2C3 clocks disabled by the clock gating
1: I2C3 clocks enabled by the clock gating
Set and cleared by software.
0: I2C2 clocks disabled by the clock gating
1: I2C2 clocks enabled by the clock gating
Set and cleared by software.
0: I2C1 clocks disabled by the clock gating
1: I2C1 clocks enabled by the clock gating
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during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
DocID024597 Rev 5
during Sleep and Stop modes
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
RM0351