Table 46. Summary Of The Dma2 Requests For Each Channel - ST STM32L4 5 Series Reference Manual

RM0351
Table 45. Summary of the DMA1 requests for each channel (continued)
Request.
Channel 1
number
2 -
3 -
4 TIM2_CH3
TIM17_CH1
5
TIM17_UP
6 TIM4_CH1
7 -

Table 46. Summary of the DMA2 requests for each channel

Request.
Channel 1
number
0 I2C4_RX
1 SAI1_A
2 UART5_TX
3 SPI3_RX
4 SWPMI1_RX SWPMI1_TX
TIM5_CH4
5
TIM5_TRIG
6 AES_IN
TIM8_CH3
7
TIM8_UP
Channel 2 Channel 3
USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX
I2C3_TX I2C3_RX
TIM16_CH1
TIM2_UP
TIM16_UP
TIM3_CH4
TIM3_CH3
TIM3_UP
TIM6_UP
-
DAC1
TIM1_CH1 TIM1_CH2
Channel 2 Channel 3
I2C4_TX ADC1
SAI1_B SAI2_A
UART5_RX UART4_TX
SPI3_TX -
SPI1_RX
TIM5_CH3
-
TIM5_UP
AES_OUT AES_OUT
TIM8_CH4
TIM8_TRIG -
TIM8_COM
DocID024597 Rev 5
Direct memory access controller (DMA)
Channel 4 Channel 5
I2C2_TX I2C2_RX
- TIM2_CH1
TIM7_UP.
QUADSPI
DAC2
TIM4_CH2 TIM4_CH3
TIM15_CH1
TIM1_CH4
TIM15_UP
TIM1_TRIG
TIM15_TRIG
TIM1_COM
TIM15_COM
Channel 4 Channel 5
ADC2 ADC3
SAI2_B -
- UART4_RX
TIM6_UP TIM7_UP
DAC1 DAC2
SPI1_TX DCMI
TIM5_CH2 TIM5_CH1
- AES_IN
SDMMC1 SDMMC1
Channel 6 Channel 7
I2C1_TX I2C1_RX
TIM16_CH1 TIM2_CH2
TIM16_UP TIM2_CH4
TIM3_CH1 TIM17_CH1
TIM3_TRIG TIM17_UP
- TIM4_UP
TIM1_UP TIM1_CH3
Channel 6 Channel 7
DCMI -
SAI1_A SAI1_B
USART1_TX USART1_RX
- QUADSPI
LPUART1_ LPUART1_
TX RX
I2C1_RX I2C1_TX
- HASH_IN
TIM8_CH1 TIM8_CH2
343/1830
356