ST STM32L4 5 Series Reference Manual page 488

Quad-SPI interface (QUADSPI)
17.6 QUADSPI registers
17.6.1 QUADSPI control register (QUADSPI_CR)
Address offset: 0x0000
Reset value: 0x0000 0000
31 30 29 28
PRESCALER
rw rw rw rw
15 14 13 12
Res. Res. Res. Res.
Bits 31: 24 PRESCALER[7:0]: Clock prescaler
Bit 23 PMM: Polling match mode
Bit 22 APMS: Automatic poll mode stop
Bit 21 Reserved, must be kept at reset value.
Bit 20 TOIE: TimeOut interrupt enable
Bit 19 SMIE: Status match interrupt enable
488/1830
27 26 25 24
rw rw rw rw
11 10 9 8
FTHRES
rw rw rw rw
This field defines the scaler factor for generating CLK based on the AHB clock
(value+1).
0: F = F , AHB clock used directly as QUADSPI CLK (prescaler bypassed)
CLK AHB
1: F = F /2
CLK AHB
2: F = F /3
CLK AHB
...
255: F = F /256
CLK AHB
For odd clock division factors, CLK's duty cycle is not 50%. The clock signal remains
high one cycle longer than it stays low.
This field can be modified only when BUSY = 0.
This bit indicates which method should be used for determining a "match" during
automatic polling mode.
0: AND match mode. SMF is set if all the unmasked bits received from the Flash
memory match the corresponding bits in the match register.
1: OR match mode. SMF is set if any one of the unmasked bits received from the Flash
memory matches its corresponding bit in the match register.
This bit can be modified only when BUSY = 0.
This bit determines if automatic polling is stopped after a match.
0: Automatic polling mode is stopped only by abort or by disabling the QUADSPI.
1: Automatic polling mode stops as soon as there is a match.
This bit can be modified only when BUSY = 0.
This bit enables the TimeOut interrupt.
0: Interrupt disable
1: Interrupt enabled
This bit enables the status match interrupt.
0: Interrupt disable
1: Interrupt enabled
DocID024597 Rev 5
23 22 21 20
PMM APMS Res. TOIE
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7 6 5 4
FSEL DFM Res. SSHIFT
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RM0351
19 18 17
SMIE FTIE TCIE TEIE
rw rw rw
3 2 1
TCEN DMAEN ABORT
rw rw rw
16
rw
0
EN
w1s