ST STM32L4 5 Series Reference Manual page 7

RM0351
6.4.12
6.4.13
6.4.14
6.4.15
6.4.16
6.4.17
6.4.18
6.4.19
6.4.20
6.4.21
6.4.22
6.4.23
6.4.24
6.4.25
6.4.26
6.4.27
6.4.28
6.4.29
6.4.30
6.4.31
6.4.32
6.4.33
7 Clock recovery system (CRS) (only valid for STM32L496xx/4A6xx
devices) 279
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
7.2 CRS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
7.3 CRS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . . . . . 240
APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . . . . . . . . . 240
APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . . . . . . . . . 243
APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 244
AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . . . . . 245
AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . . . . . 247
AHB3 peripheral clock enable register(RCC_AHB3ENR) . . . . . . . . . . 248
APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . . . . 249
APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . . . . 252
APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 254
AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
APB1 peripheral clocks enable in Sleep and Stop modes register 1
(RCC_APB1SMENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
APB1 peripheral clocks enable in Sleep and Stop modes register 2
(RCC_APB1SMENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_APB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Peripherals independent clock configuration register (RCC_CCIPR) . 265
Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 268
Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Clock recovery RC register (RCC_CRRCR) . . . . . . . . . . . . . . . . . . . . 272
Peripherals independent clock configuration register (RCC_CCIPR2) 273
RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Synchronization input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Frequency error measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Frequency error evaluation and automatic trimming . . . . . . . . . . . . . . 282
CRS initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
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