Table 56. Dma2D Register Map And Reset Values - ST STM32L4 5 Series Reference Manual

Chrom-Art Accelerator™ controller (DMA2D)
12.5.24 DMA2D register map
The following table summarizes the DMA2D registers. Refer to
the DMA2D register base address.
Offset Register
DMA2D_CR
0x0000
Reset value
DMA2D_ISR
0x0004
Reset value
DMA2D_IFCR
0x0008
Reset value
DMA2D_FGMAR
0x000C
Reset value
DMA2D_FGOR
0x0010
Reset value
DMA2D_BGMAR
0x0014
Reset value
DMA2D_BGOR
0x0018
Reset value
DMA2D_FGPFCCR
0x001C
Reset value
DMA2D_FGCOLR
0x0020
Reset value
DMA2D_BGPFCCR
0x0024
Reset value
DMA2D_BGCOLR
0x0028
Reset value
DMA2D_FGCMAR
0x002C
Reset value
DMA2D_BGCMAR
0x0030
Reset value
DMA2D_OPFCCR
0x0034
Reset value
390/1830

Table 56. DMA2D register map and reset values

0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
ALPHA[7:0]
0 0 0 0 0 0 0 0
0
ALPHA[7:0]
0 0 0 0 0 0 0 0
0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
DocID024597 Rev 5
0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
RED[7:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
RED[7:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
0 0
Section 2.2.2 on page 75
0 0 0 0 0 0
0
0
0 0 0 0 0 0 0 0 0
LO[13:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
LO[13:0]
0 0 0 0 0 0 0 0 0
CS[7:0]
0 0 0 0 0 0 0
GREEN[7:0]
0 0 0 0 0 0 0 0 0
CS[7:0]
0 0 0 0 0 0 0
GREEN[7:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
RM0351
for
0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
CM[3:0]
0 0 0 0 0
BLUE[7:0]
0 0 0 0 0
CM[3:0]
0 0 0 0 0
BLUE[7:0]
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
CM[2:0]
0 0 0